Wafer Level Chip Size Package Redistribution Layers

Solution Overview

Problem

The complexity and increased manufacturing costs of wafer level chip size packages (WLCSPs) arise from the need for multiple redistribution layers and passivation layers to form complicated circuits, leading to electrical shorts and inefficiencies in circuit formation.

Innovation Solution

The formation of lands at the ends of redistribution layers, covered by a second dielectric layer, with a first under bump metallurgy (UBM) layer and a second UBM layer that serves as a ground or power plane, allowing for electrical connection between physically separated redistribution layers without shorts, and providing a shield against electromagnetic interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If two or more RDL layers are used to form complicated circuits, then circuit complexity is improved, but packaging complexity and manufacturing costs increase

Engineering Contradiction:
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple RDL layers by allowing RDL traces to cross over each other in the same plane using bridge structures. This eliminates the need for multiple stacked RDL layers, reducing packaging complexity while maintaining the ability to form complicated circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent transitions from a vertical stacking approach (multiple RDL layers in different planes) to a horizontal approach (multiple RDL traces crossing in the same plane). This dimensional change allows complex circuit routing without increasing packaging complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If two or more RDL layers are used to form complicated circuits, then circuit complexity is improved, but manufacturing costs increase

Engineering Contradiction:
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple RDL routing functions into a single RDL layer, reducing the number of manufacturing steps required for depositing and patterning multiple layers. This simplification directly reduces manufacturing costs while maintaining circuit complexity capabilities.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple RDL layers are used, then circuit functionality is improved, but electrical shorts between layers increase

Engineering Contradiction:
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent eliminates the need for multiple RDL layers by enabling trace crossing in the same plane, thereby removing the interfaces between layers where electrical shorts could occur. This improves reliability while maintaining circuit functionality.

Inventive Principle:
Principle #5Merging (Combining)

4Area of stationary object

If the second UBM layer is widely formed on the second dielectric layer, then ground plane area is improved, but material usage increases

Engineering Contradiction:
Core Design Contradiction:
Area of stationary objectVSQuantity of substance

Solution Approach 1:

The second UBM layer serves multiple functions simultaneously: it provides a large-area ground plane for signal reference, acts as an electromagnetic shield, and serves as a heat dissipation path. This multi-functionality justifies the material usage by delivering multiple benefits from a single structural element.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent converts what could be considered excess material usage into a beneficial electromagnetic shield and heat dissipation structure. The widely-formed second UBM layer, which might appear as material waste, actually provides protective and functional benefits that enhance overall device performance.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS7977783B1Wafer level chip size package having redistribution layers
Publication Date: 2011.07.12
  • US7977783B1 patent drawing
  • US7977783B1 patent drawing
  • US7977783B1 patent drawing

AI summary

A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.