WLCSP TSV Vertical Integration for Package-on-Package
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Solution Overview
Problem
There is a need for efficient vertical integration of semiconductor devices in package-on-package (PoP) structures compatible with wafer-level chip scale packages (WLCSPs, which is complex and increases production costs due to the complexity of device integration and package laminate.
Innovation Solution
The method involves forming conductive layers over semiconductor die, creating through-silicon vias (TSVs) through the WLCSP, and electrically connecting semiconductor components using bumps and interconnect structures to achieve vertical integration, allowing for the stacking and interconnection of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV interposer and solder bump on wire bond die are used for vertical z-direction interconnection in PoP arrangement, then electrical interconnection between WLCSP and external devices is achieved, but device integration complexity increases and package laminate costs increase
Solution Approach 1:
The patent extracts and removes the TSV interposer from the PoP structure, replacing it with direct TSV formation through the WLCSP substrate. This eliminates the intermediate interposer layer and its associated complexity while maintaining the vertical interconnection function through direct copper TSVs formed through the package substrate.
Solution Approach 2:
The patent merges the interposer function directly into the WLCSP substrate by forming TSVs through the package substrate itself. The substrate simultaneously serves as the package body and the interconnection medium, combining multiple functions into a single integrated structure that reduces overall device complexity.
2Reliability
If TSV interposer and solder bump on wire bond die are used for vertical z-direction interconnection in PoP arrangement, then electrical interconnection between WLCSP and external devices is achieved, but package laminate production costs increase
Solution Approach 1:
The patent removes the expensive TSV interposer layer from the PoP structure, replacing it with direct TSV formation through the WLCSP substrate. This elimination of the interposer layer directly reduces material costs and simplifies the laminate structure, leading to lower production costs while maintaining electrical interconnection reliability.
Solution Approach 2:
The patent uses the WLCSP substrate itself as the interconnection medium instead of requiring a separate, expensive interposer layer. The substrate performs dual functions as both the package body and the interconnection carrier, reducing overall material costs and simplifying manufacturing.
3Productivity
If smaller die size is achieved through front-end process improvements, then power consumption decreases and performance increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar die scaling to three-dimensional vertical integration by forming TSVs through the package substrate. This allows continued functionality improvement through vertical stacking rather than horizontal scaling, enabling smaller effective device footprint without requiring increasingly precise front-end manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration process, reduces production costs, and enables efficient vertical interconnection of semiconductor devices within PoP structures, enhancing the performance and reliability of semiconductor packages.
Implementation Method 1
forming first and second conductive layers over first and second opposing surfaces of the semiconductor die
Implementation Method 2
The TSVs and THVs are then filled with another conductive material, for example, by copper deposition through an electroplating process
Implementation Method 3
forming a first bump over the first conductive layer, and mounting a second semiconductor component to the first bump
Data Source
AI summary
A semiconductor wafer has a plurality of semiconductor die. First and second conductive layers are formed over opposing surfaces of the semiconductor die, respectively. Each semiconductor die constitutes a WLCSP. A TSV is formed through the WLCSP. A semiconductor component is mounted to the WLCSP. The first semiconductor component is electrically connected to the first conductive layer. A first bump is formed over the first conductive layer, and a second bump is formed over the second conductive layer. An encapsulant is deposited over the first bump and first semiconductor component. A second semiconductor component is mounted to the first bump. The second semiconductor component is electrically connected to the first semiconductor component and WLCSP through the first bump and TSV. A third semiconductor component is mounted to the first semiconductor component, and a fourth semiconductor component is mounted to the third semiconductor component.