Wafer Level Package Structure With 3D Bump Redistribution
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Solution Overview
Problem
Conventional semiconductor packaging technologies face challenges in increasing I/O pad density due to smaller die sizes, limited fan-out capabilities, and high alignment requirements, which affect yield and reliability.
Innovation Solution
A method involving the formation of copper bumps on semiconductor dies, self-alignment during packaging, and the use of redistribution traces and molding compounds to create a robust fan-out package structure, allowing for increased I/O pad density and improved alignment accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional WLP is used with smaller die sizes, then throughput is improved and cost is reduced, but the number of I/O pads is limited due to pitch constraints and solder bridge risks
Solution Approach 1:
The patent transitions from a planar 2D pad layout to a 3D vertical structure by forming bumps on the die surface and redistributing them in multiple layers. This allows I/O pads to be stacked vertically and redistributed to a larger area, increasing the number of I/O pads beyond the limits of conventional single-layer fan-in packaging.
Solution Approach 2:
The patent implements multi-layer bump structures where bumps are formed on the die surface, then encapsulated in molding compound, and additional bumps are formed on top of the first layer. This nested arrangement allows multiple layers of I/O pads to be stacked vertically, effectively increasing the total number of I/O pads within a compact footprint.
2Quantity of substance
If I/O pad pitch is decreased to increase pad density, then more pads can be packed, but solder bridges may occur reducing reliability
Solution Approach 1:
By transitioning from 2D to 3D bump structures with vertical height, the patent increases the spacing between adjacent pads in the vertical dimension. This allows closer horizontal spacing while maintaining adequate solder joint separation, enabling higher pad density without solder bridges.
Solution Approach 2:
The patent changes the physical parameters of the connection structure by forming elevated bumps with controlled height and diameter ratios. This modifies the solder joint geometry, allowing reduced pitch while maintaining reliability by preventing solder bridges through the increased vertical separation.
3Quantity of substance
If fan-out chip packages are used to increase I/O pad area, then the number of I/O pads is increased, but the package size and pitch become significantly greater
Solution Approach 1:
The patent stacks multiple layers of bumps vertically within the molding compound, with each layer containing I/O pads. This vertical nesting allows the package to maintain a compact footprint while accommodating a large number of I/O pads across multiple layers, avoiding the significant area expansion of conventional fan-out packages.
Solution Approach 2:
The patent redistributes I/O pads from a single large planar area to multiple smaller layers stacked vertically. This transforms the area requirement from a 2D expansion to a 3D vertical arrangement, maintaining a compact package footprint while increasing the total number of I/O pads.
4Reliability
If dies are aligned to connecting portions with high accuracy, then package reliability is improved, but manufacturing complexity and time increase
Solution Approach 1:
The patent implements self-aligned bump formation where the bump structure itself provides alignment references. The bumps are formed directly on the die surface with precise positioning, and the molding compound encapsulation preserves this alignment. This self-aligning feature reduces the need for complex external alignment processes while maintaining high accuracy.
Solution Approach 2:
The patent performs preliminary alignment by forming bumps with precise positions on the die surface before packaging. This pre-established alignment reference simplifies subsequent packaging steps, as the bump locations serve as built-in alignment markers that guide the connection process without requiring complex real-time alignment mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances I/O pad density, reduces damage to semiconductor chips, and improves alignment accuracy, leading to increased packaging efficiency and yield while maintaining reliability.
Implementation Method 1
reflowing the solder balls so that the plurality of dies are attached to the chip carrier
Data Source
AI summary
A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.