Wafer Level Package Exposed Lead Tip for Board Reliability
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Solution Overview
Problem
Wafer-level QFN packages face challenges with high production costs and low pin counts, and their solder joints are often not inspectable, leading to reduced board level reliability compared to leadframe QFN packages.
Innovation Solution
A wafer level package is developed with an exposed lead tip and a solder buttress structure, optimized for enhanced board level reliability and easy visual inspection, featuring a processed semiconductor wafer with integrated circuit dies, metal pads, dielectric layers, redistribution layers, pillars, and a plating layer, allowing for improved solder fillet formation and connection strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wafer-level QFN packaging technology is used, then production cost is reduced and chip size is minimized, but solder joint inspectability is lost and board level reliability decreases
Solution Approach 1:
The patent introduces a vertical dimension by forming elevated solder buttress structures that rise above the package substrate surface. This dimensional change allows solder joints to be visually inspected from the side, solving the inspectability problem while maintaining the reliability benefits of wafer-level packaging.
Solution Approach 2:
The patent segments the solder connection structure into distinct components: the base solder joint and the elevated solder buttress. This segmentation allows the buttress portion to serve as a visual indicator for inspection while the base joint provides the primary electrical and mechanical connection.
2Productivity
If wafer-level QFN packaging technology is used, then production cost is reduced, but pin count is limited
Solution Approach 1:
The patent utilizes the vertical dimension to add solder buttress structures that provide additional connection points without increasing the horizontal footprint. This enables higher effective pin count and connectivity options while maintaining the cost advantages of wafer-level packaging.
3Ease of manufacture
If traditional wafer-level QFN packages are used, then manufacturing is simplified, but solder connection strength is reduced
Solution Approach 1:
The patent incorporates solder buttress structures during the wafer-level packaging manufacturing process itself, before the package is mounted on the board. This preliminary formation of strengthened solder connections simplifies the overall manufacturing process while ensuring robust solder joints from the outset.
Solution Approach 2:
The patent creates a composite solder structure combining the base solder material with elevated buttress formations, potentially using different material compositions or structures in different regions to optimize both connection strength and manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances board level reliability and facilitates easy visual inspection by creating an exposed lead tip that strengthens solder connections and increases the surface area for solder adhesion, addressing the limitations of traditional wafer-level QFN packages.
Implementation Method 1
forming a plating layer on the pillar layer
Data Source
AI summary
A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability.