Wafer Level Package Heterogeneous Integration Horizontal PPI
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Solution Overview
Problem
Existing wafer-level package (WLP) techniques for heterogeneous integration technologies often require vertical stacking, which may not be feasible in all situations due to height constraints, necessitating the development of alternative packaging methods that maintain high density and performance.
Innovation Solution
A WLP device comprising a first chip made of one technology and a second chip made of another, packaged together using a molding material with post passivation interconnect (PPI) lines connecting contact pads on each chip, allowing for horizontal integration and electrical connectivity through solder balls or other connection devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical stacking is used for heterogeneous integration, then integration density is improved, but package height increases
Solution Approach 1:
The patent transitions from vertical stacking (3D stacking) to horizontal arrangement (2D planar integration) of chips on the substrate. This dimensional change allows multiple chips to be integrated on the same plane without increasing package height, resolving the contradiction between integration density and package height by utilizing the lateral dimension instead of the vertical dimension.
2Quantity of substance
If more chips are integrated in a given area, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated system into separate chips that are individually manufactured using standard processes, then packaged together on a substrate. Each chip maintains its own passivation layer and contact pads, allowing independent fabrication and testing before final assembly. This segmentation reduces manufacturing complexity by avoiding the need to create highly complex monolithic structures while achieving high integration density through multi-chip packaging.
3Adaptability or versatility
If heterogeneous technologies are integrated, then functionality and performance are improved, but package size increases
Solution Approach 1:
The patent combines multiple chips with heterogeneous technologies (different materials, processes, or functions) onto a single package substrate with shared interconnect structures and common packaging. This merging approach allows diverse functionalities to be integrated in a compact form factor, reducing the overall package size compared to separate packaging while maintaining the benefits of heterogeneous integration.
Data Source
AI summary
Methods and apparatus are disclosed to form a WLP device that comprises a first chip made of a first technology, and a second chip made of a second technology different from the first technology packaged together by a molding material encapsulating the first chip and the second chip. A post passivation interconnect (PPI) line may be formed on the molding material connected to a first contact pad of the first chip by a first connection, and connected to a second contact pad of the second chip by a second connection, wherein the first connection and the second connection may be a Cu ball, a Cu via, a Cu stud, or other kinds of connections.