Wafer Level Package Molding Without Grinding

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Solution Overview

Problem

The complexity and difficulty in selecting materials for molding members in wafer level package fabrication, which requires a grinding process, complicate semiconductor manufacturing and limit the integration of semiconductor devices in electronic products.

Innovation Solution

A method of fabricating a wafer level package where a molding member is dispensed and pressurized to expose the top surface of semiconductor chips without grinding, allowing for the selection of a molding member based on calculated volume and density, and using a release film to facilitate the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a grinding process is used to fabricate wafer level package, then the top surface of semiconductor chips can be exposed, but the manufacturing process becomes complicated and material selection for molding member becomes difficult

Engineering Contradiction:
Improveexposure of top surface of semiconductor chipsVSAvoidcomplexity of manufacturing process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention extracts and eliminates the grinding process from the manufacturing sequence. Instead of grinding the molding member to expose chip surfaces, the method directly forms the molding member with the appropriate height during the molding process itself, removing the complex post-processing step while maintaining the desired exposure of semiconductor chip top surfaces

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention performs preliminary action by pre-calculating and pre-setting the height of the molding member before the molding process. The molding member is formed with a predetermined height that directly exposes the top surfaces of semiconductor chips, eliminating the need for subsequent grinding operations and simplifying the entire manufacturing process

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If a grinding process is used to fabricate wafer level package, then the top surface of semiconductor chips can be exposed, but it is very difficult to select material for the molding member

Engineering Contradiction:
Improveexposure of top surface of semiconductor chipsVSAvoidmaterial selection for molding member
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The invention changes the critical parameter from post-molding height adjustment (grinding) to pre-molding height control. By controlling the height parameter during the molding process itself, the method allows versatile material selection since the height can be precisely controlled through molding parameters rather than requiring materials that are easy to grind

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention makes the molding process multi-functional by combining the molding operation with the height-setting operation. The molding member is formed with the final required height in a single process step, allowing any material that can be molded to the specified dimensions to be used, thereby expanding material selection versatility

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If grinding process is eliminated, then manufacturing complexity is reduced, but precise control of molding member height is required

Engineering Contradiction:
Improvecomplexity of manufacturing processVSAvoidheight control of molding member
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The invention performs preliminary calculation and planning of the molding member height before the molding process. The height is predetermined based on the semiconductor chip dimensions and packaging requirements, allowing precise control to be achieved through pre-planned molding parameters rather than post-process adjustment

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention replaces the mechanical grinding system with a controlled molding system. Instead of using mechanical removal of material (grinding) to achieve precise height, the method uses controlled material deposition and curing during molding, substituting a more precise and controllable process that achieves the same dimensional accuracy

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the complexity and cost of the manufacturing process, allows for the selection of more reliable molding members, and minimizes stress and warpage due to thermal expansion differences, while avoiding the need for grinding, thus enhancing the reliability and efficiency of wafer level package fabrication.

Implementation Method 1

pressurizing the molding member by using a plunger so as to fabricate a wafer level package

Methodology Applied
Scientific EffectCompression: Compression

Implementation Method 2

attaching a release film to a bottom surface of the plunger

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS8940557B2Method of fabricating wafer level package
Publication Date: 2015.01.27 SAMSUNG ELECTRONICS CO LTD
  • US8940557B2 patent drawing
  • US8940557B2 patent drawing
  • US8940557B2 patent drawing

AI summary

A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.