Wafer-Level Packaging Post Passivation for Fine Pitch and Stress Relief
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Solution Overview
Problem
Current Wafer-Level Packaging (WLP) technologies face challenges in achieving fine pitch contact structures and adequate stress relief in semiconductor devices, limiting the scale of integration and reliability due to the limitations of existing post passivation structures and processes.
Innovation Solution
The proposed solution involves a circuit structure with multiple metallic posts on a semiconductor substrate, where the spacing between posts is reduced to less than 250µm, and a combination of thin and thick polymer layers for stress relief, allowing for both fine pitch rerouting and improved structural reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick polymeric layer is used to provide stress relief, then stress relief is improved, but pitch resolution deteriorates due to inability to achieve high-resolution lithography
Solution Approach 1:
The patent divides the single thick polymeric layer into two separate polymeric layers: a first polymeric layer (30-100 µm) for stress relief and a second polymeric layer (5-20 µm) for supporting fine pitch lithography. This segmentation allows each layer to optimize its thickness for its specific function, resolving the contradiction between stress relief and pitch resolution.
2Manufacturing precision
If the bottom polymeric layer is made thin to reduce lateral RDL displacements, then manufacturing precision is improved, but stress relief deteriorates
Solution Approach 1:
The patent segments the polymeric support structure into two distinct layers with different thicknesses optimized for different functions. The first (bottom) layer is thinner (5-20 µm) to minimize lateral displacement and provide precise positioning, while the second (top) layer is thicker (30-100 µm) to provide adequate stress relief. This resolves the contradiction by assigning different thickness requirements to different functional layers.
3Ease of manufacture
If post passivation structures are used to enlarge pad pitch, then ease of manufacture is improved, but device complexity increases due to additional layers and processes
Solution Approach 1:
The patent designs the polymeric layers to serve multiple functions simultaneously: mechanical stress relief, lateral displacement control, lithographic support, and electrical isolation. This multi-functionality reduces the need for additional separate structures and processes, thereby easing manufacture while managing device complexity.
Data Source
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Figure 4b~6a
AI summary
A circuit structure includes a semiconductor substrate, first and second metallic posts over the semiconductor substrate, an insulating layer over the semiconductor substrate and covering the first and second metallic posts, first and second bumps over the first and second metallic posts or over the insulating layer. The first and second metallic posts have a height of between 20 and 300 microns, with the ratio of the maximum horizontal dimension thereof to the height thereof being less than 4. The distance between the center of the first bump and the center of the second bump is between 10 and 250 microns.