Wafer Level Package Sealing Frames with Coupling Portions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wafer level package techniques face stress-related sealing failures and reduced reliability during chip cutting due to the absence of gaps in solder bonding portions, leading to potential defects and reduced non-defective rates.
Innovation Solution
A wafer level package design featuring sealing frames spaced apart with coupling portions that connect their corners, allowing for reduced stress during cutting by adjusting the length and width of the coupling portions, and using arc-shaped corner portions to independently manage the dicing line width, thereby minimizing stress and waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If solder bonding portions are formed without gaps to partition electronic devices on the wafer, then device density is improved, but stress concentration during cutting causes sealing failure and reduced reliability
Solution Approach 1:
The patent introduces gaps between adjacent solder bonding portions, dividing the continuous bonding structure into segmented sections. This segmentation allows the dicing blade to pass through without concentrating stress on the sealing frames, thereby preventing sealing failure while maintaining device density on the wafer.
Solution Approach 2:
The patent extracts or removes the continuous solder bonding material between adjacent devices, creating gaps in the bonding portions. This extraction eliminates the stress concentration path that would otherwise transmit cutting forces to the sealing frames, protecting them from damage during the dicing process.
2Productivity
If sealing frames are positioned close together to maximize chip utilization, then wafer utilization is improved, but stress during cutting increases causing potential defects
Solution Approach 1:
By segmenting the solder bonding portions with gaps, the patent enables tighter spacing of sealing frames without increasing cutting stress. The gaps act as stress relief zones that allow the dicing blade to pass through, permitting higher wafer utilization while maintaining acceptable stress levels during cutting.
3Strength
If continuous solder bonding portions are used to ensure strong bonding, then bonding strength is improved, but cutting stress concentrates on sealing frames causing sealing failure
Solution Approach 1:
The patent segments the solder bonding portions by introducing gaps between adjacent bonding sections. Each segmented bonding portion maintains sufficient bonding strength for its associated device, while the gaps prevent stress concentration from propagating across multiple sealing frames during the cutting process.
Solution Approach 2:
The patent applies different properties to different regions: the solder bonding portions maintain strong bonding characteristics locally at each device, while the gap regions provide stress relief properties. This local differentiation allows strong bonding where needed while preventing stress concentration in critical sealing areas.
Data Source
AI summary
A wafer level package that includes a first wafer; a second wafer facing the first wafer; a plurality of chips between the first wafer and the second wafer and arranged in an array; a plurality of sealing frames at predetermined intervals and surrounding each of the plurality of chips to seal the chips; and a coupling portion which couples opposed corners of respective sealing frames.