Wafer-Level SiP Shielding Housing for Magnetic Interference
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Solution Overview
Problem
Conventional wafer-level system-in-package (WLSiP) packaging technologies face challenges in reducing the volume and thickness of integrated circuits while effectively shielding against external magnetic fields, as existing shielding structures are bulky and affect all chips, rather than just those susceptible to interference.
Innovation Solution
A WLSiP packaging method involving a bonding structure with a device wafer and chips, an encapsulation layer, and a trench filled with conductive material forming a shielding housing around susceptible chips, which includes a conductive sidewall and layer above the chip, reducing magnetic interference without increasing the overall package thickness or volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If shielding structures are provided in integrated circuits to reduce external magnetic field interference, then magnetic field shielding effectiveness is improved, but volume and thickness increase
Solution Approach 1:
The patent divides the wafer into multiple regions, with shielding structures only formed around specific chips that are susceptible to magnetic field interference (such as memory chips), while other chips without shielding needs do not have shielding structures. This selective segmentation approach provides magnetic shielding where needed while avoiding unnecessary volume increase for other components.
Solution Approach 2:
The patent implements local quality by providing different structural characteristics to different regions of the wafer. Specifically, shielding structures (conductive layers or conductive enclosures) are localized only around chips requiring magnetic field protection, while other regions maintain their original compact structure without additional shielding materials, thus optimizing the balance between shielding effectiveness and package size.
2Object-affected harmful factors
If shielding structures are provided in integrated circuits to reduce external magnetic field interference, then magnetic field shielding effectiveness is improved, but package thickness increases
Solution Approach 1:
The patent segments the wafer thickness dimension by forming shielding structures only in specific local regions around susceptible chips, rather than providing uniform shielding across the entire wafer thickness. This allows the package thickness to be minimized while still providing adequate shielding where required.
Solution Approach 2:
The patent applies local quality by varying the structural characteristics in the thickness direction - shielding structures (such as conductive layers or enclosures) are introduced only in regions where magnetic field protection is needed, while other regions maintain the minimum necessary thickness, thus reducing the overall package thickness while maintaining shielding effectiveness for vulnerable components.
3Object-affected harmful factors
If conventional shielding structures are used for all chips, then magnetic field shielding is provided, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the wafer into shielded and non-shielded regions based on the specific magnetic field susceptibility of different chips. This segmentation allows for simplified manufacturing processes where shielding structures are formed only in necessary locations, reducing overall device complexity and easing manufacturing requirements compared to providing shielding for every chip regardless of need.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively shields specific chips from external magnetic fields while minimizing the package's volume and thickness, enhancing the stability and reliability of integrated circuits without adding bulk.
Implementation Method 1
forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, and the shielding housing including a conductive sidewall formed in the trench
Data Source
AI summary
Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall.