Word-Line Conductive Layers with Air Gaps for Capacitance Reduction
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Solution Overview
Problem
Conventional three-dimensional semiconductor storage devices with SGT structure face issues of increased parasitic capacitance and resistance in word-line conductive layers, leading to delays in device operation due to voltage potential differences between ends of the conductive layers.
Innovation Solution
A non-volatile semiconductor storage device with memory strings featuring columnar semiconductor layers, charge accumulation layers, and conductive layers with air gaps between them, along with a manufacturing method involving alternately laminated sacrifice layers and conductive layers, forming insulation layers and removing sacrifice layers to reduce capacitive coupling and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If word-line conductive layers are made thinner to ease processing or increase the number of laminated layers, then ease of manufacture is improved, but resistance in the word-line conductive layers increases
Solution Approach 1:
The patent uses a composite structure for the conductive layer comprising a first conductive layer and a second conductive layer with different materials and properties. The first conductive layer provides low resistance, while the second conductive layer provides planarization and structural support, achieving both low resistance and ease of processing without compromising reliability
2Device complexity
If word-line conductive layers are made thinner to increase the number of laminated layers, then device integration is improved, but resistance in the word-line conductive layers increases
Solution Approach 1:
The conductive layer is constructed as a composite of multiple sub-layers with different functions. The first conductive layer (e.g., polysilicon or metal) provides low resistance for electrical signals, while the second conductive layer (e.g., spin-on-glass or spin-on-glass-like material) provides planarization and mechanical support, enabling thin design without excessive resistance
3Device complexity
If opposite arrangement of word-line conductive layers is maintained, then device structure is simplified, but parasitic capacitance between word-line conductive layers increases
Solution Approach 1:
The patent introduces an air gap as an intermediary layer between the first and second conductive layers. This air gap acts as a mediator that reduces parasitic capacitance coupling between the conductive layers while maintaining the opposite arrangement structure, thus preserving structural simplicity while reducing harmful capacitive effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces capacitive coupling and resistance in word-line conductive layers, minimizing voltage boosting time differences and enhancing the operational efficiency of the semiconductor storage device.
Implementation Method 1
air gaps being formed between the first conductive layers located there above and there below... reduces capacitive coupling and resistance in word-line conductive layers
Data Source
AI summary
A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprises: a first columnar semiconductor layer extending in a vertical direction to a substrate; a charge accumulation layer formed around the first columnar semiconductor layer via a first insulation layer; and a first conductive layer formed around the charge accumulation layer via a second insulation layer. Each of the first conductive layers is formed to expand in a two-dimensional manner, and air gaps are formed between the first conductive layers located there above and there below.