Configurable Word Line Driver Circuit for Flash Memory Bias Testing

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Solution Overview

Problem

The existing methods for testing and adjusting word line bias patterns in flash memory devices require hardware changes, which are costly and time-consuming, as the patterns are 'hard-wired' into metal masks, necessitating new prototypes for each pattern change.

Innovation Solution

A word line driver circuit with a register that can be loaded with different bias patterns, allowing test engineers to adjust and test various bias patterns without hardware changes, using a decoder and multiplexer to configure the driver circuit to apply specific voltages to word lines during programming, read, or erase operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If word line bias patterns are hard-wired into metal masks, then manufacturing precision is maintained, but device complexity increases and adaptability decreases

Engineering Contradiction:
Improvebias pattern precisionVSAvoidbias pattern flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent transforms static hard-wired bias patterns into dynamic configurable patterns by introducing a register that can be loaded with different bias pattern data. This allows the word line driver circuit to adaptively apply different bias patterns during testing without hardware changes, resolving the contradiction between manufacturing precision and adaptability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent enables changing the bias pattern parameters through software configuration rather than hardware modification. By loading different values into the register, various bias patterns can be tested while maintaining manufacturing precision through controlled application of voltages to word lines.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If hardware changes are made to test different bias patterns, then adaptability improves, but loss of time and productivity decrease

Engineering Contradiction:
Improvebias pattern varietyVSAvoidprototype development time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent creates a software-based copy mechanism where bias patterns are stored as data in a register rather than being physically hard-wired. This allows rapid copying and switching between different bias patterns through data loading, eliminating the time-consuming process of creating new hardware prototypes for each pattern variation.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If hardware changes are made for each bias pattern, then adaptability improves, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvetesting flexibilityVSAvoidhardware configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal word line driver circuit that can handle multiple bias patterns through a single configurable register. This multi-functional approach allows the same hardware to perform various testing configurations, reducing overall device complexity while maintaining high adaptability for different testing scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10332603B2Access line management in a memory device
Publication Date: 2019.06.25 MICRON TECHNOLOGY INC
  • US10332603B2 patent drawing
  • US10332603B2 patent drawing
  • US10332603B2 patent drawing

AI summary

Memory devices including an array of memory cells, a plurality of access lines selectively coupled to respective pluralities of memory cells of the array of memory cells, a plurality of first registers, a second register, a first multiplexer, a second multiplexer, and a decoder configured to selectively connect a corresponding access line to a selected voltage source of a plurality of voltage sources in response to the output of the second multiplexer, wherein the second multiplexer is configured to pass a selected one of the output of the second register and the output of the first multiplexer to its output, and wherein the first multiplexer is configured to pass a selected one of the outputs of the plurality of first registers to its output.