Word Line Placement in M3 Metal Layer for Memory Cell RC Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As process geometries shrink, moving word lines into M1 or M2 layers increases the RC value, slowing down memory access and increasing power consumption due to high capacitive coupling with power conductors.
Innovation Solution
Placing word lines in M3 or higher metal layers and depopulating power conductors within the same layer to reduce capacitive coupling, allowing for wider word lines adjacent interstitial gaps, thereby decreasing the RC value and improving memory cell speed and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If word lines are moved into M1 or M2 layers to accommodate smaller via spacings, then the constraint upon minimum via spacing is addressed, but the RC value associated with the word lines increases, slowing down memory accesses and increasing power consumption
Solution Approach 1:
The patent moves word lines from lower metal layers (M1/M2) to higher metal layers (M3 and above), utilizing the vertical dimension of the multi-layer metal structure. This dimensional transition allows word lines to be positioned where via spacing constraints are more relaxed while maintaining acceptable RC values, thereby resolving the contradiction between manufacturing precision requirements and memory access speed.
2Manufacturing precision
If word lines are placed in M1 or M2 layers, then via spacing constraints are satisfied, but capacitive coupling with power conductors increases, leading to higher power consumption
Solution Approach 1:
By transitioning word lines to higher metal layers (M3+), the patent increases the vertical separation between word lines and power conductors. This dimensional separation reduces capacitive coupling effects, thereby decreasing power consumption while still satisfying via spacing constraints through the multi-layer architecture.
3Device complexity
If power conductors are kept continuous in the same layer as word lines, then power distribution is simplified, but capacitive coupling with word lines increases, increasing RC value and reducing speed
Solution Approach 1:
The patent segments continuous power conductors into separate power line sections within the same metal layer containing word lines. These segmented power lines are spaced apart and parallel to word lines, reducing capacitive coupling while maintaining adequate power distribution. The segmentation strategy balances structural simplicity with performance requirements by creating multiple discrete power delivery paths rather than a single continuous conductor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the RC value associated with word lines, enhancing memory cell speed and reducing power consumption while accommodating smaller via spacings, thus addressing the constraints of shrinking process geometries.
Implementation Method 1
depopulated so as to reduce the capacitive coupling between the word line and the power conductors
Data Source
AI summary
A memory cell 6 includes a M3 metal layer which incorporate continuous word lines 12 and power conductors formed of a plurality of separate power line sections 14 running parallel to the word lines. Interstitial gaps between the separate power line sections are larger in size than the power line sections themselves. The power line sections are disposed in a staggered arrangement either side of the word lines.