Semiconductor Storage Device Word Line Voltage Management

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Solution Overview

Problem

High integration of semiconductor storage devices is hindered by the difficulty in effectively reducing the size of memory cells and their intercellular gaps, leading to potential erroneous data storage in adjacent cells during writing operations.

Innovation Solution

The semiconductor storage device employs a voltage management strategy where a voltage higher than the selected voltage but different from the non-selected voltage is applied to adjacent word lines during writing operations, ensuring the select transistor of the selected memory cell is turned off while adjacent memory cell transistors are weakly turned on, preventing heat transfer and erroneous writing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the size of memory cells and their gaps is reduced to achieve high integration, then integration density is improved, but erroneous data storage in adjacent cells occurs during writing operations

Engineering Contradiction:
Improveintegration densityVSAvoiddata storage accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies different voltage levels to different word lines based on their position relative to the selected memory cell. Specifically, the selected word line receives a first voltage level, adjacent word lines receive a second voltage level (higher than first), and non-selected word lines receive a third voltage level (lower than first). This localized differentiation of voltage conditions allows smaller cell gaps while preventing erroneous writing in adjacent cells, as the intermediate voltage on adjacent word lines keeps their transistors weakly turned on without fully conducting.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the voltage parameter applied to word lines during writing operations to solve the contradiction. By dynamically adjusting voltage levels on different word lines (first voltage for selected, second higher voltage for adjacent, third lower voltage for non-selected), the system enables smaller memory cell gaps while maintaining data storage accuracy. The voltage parameter modification creates distinct operational states that prevent crosstalk between adjacent cells.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If a higher voltage is applied to selected word line to ensure proper writing, then writing reliability is improved, but heat transfer to adjacent cells increases causing erroneous writing

Engineering Contradiction:
Improvewriting operation reliabilityVSAvoidheat transfer to adjacent cells
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediate voltage level (second voltage) for adjacent word lines that acts as a mediator between the high voltage (first voltage) on the selected word line and the low voltage (third voltage) on non-selected word lines. This intermediate voltage keeps adjacent cell transistors weakly turned on, creating a buffer zone that prevents heat and current from the selected cell from causing erroneous writing in adjacent cells, while still allowing the selected cell to write properly at high voltage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary protective action by setting the adjacent word lines to an intermediate voltage level before the writing operation on the selected cell. This pre-established voltage condition creates a protective state that prevents heat transfer and current leakage from affecting adjacent cells during the high-voltage writing operation, thereby preventing erroneous writing before it can occur.

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for a reduction in the size of memory cells and their gaps, enhancing integration density while preventing erroneous data storage in adjacent cells, thus enabling effective high integration of the semiconductor storage device.

Implementation Method 1

changing the variable resistance element to a high resistance state (reset state) or a low resistance state (set state)

Methodology Applied
Scientific EffectVariable resistance effect: Electrical Resistance

Implementation Method 2

turning off a transistor of a selected memory cell, causing a current to flow through the variable resistance element

Methodology Applied
Scientific EffectElectrical conduction control: Conduction (electrical)

Data Source

PatentUS11373703B2Semiconductor storage device
Publication Date: 2022.06.28 KIOXIA CORP
  • US11373703B2 patent drawing
  • US11373703B2 patent drawing
  • US11373703B2 patent drawing

AI summary

During a writing operation to change a resistance of a part of a variable resistance material film facing a first word line, the semiconductor storage device applies a first voltage to the first word line, applies a second voltage to a second word line, and applies a third voltage to a third word line. The first, second, and third word lines are stacked above a substrate. The second word line is adjacent to the first word line in the stacking direction. The third word line is not adjacent to the first word line in the stacking direction.