Word Line Voltage Pre-Charging for Fast Memory Read
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Nonvolatile semiconductor memory devices with multi-level cell architecture face challenges in achieving fast start-up times for word line voltages, leading to reading errors and difficulties in securing sufficient margin due to increased capacitance and voltage delays, which can be addressed by conventional methods that either increase read cycle time or require additional layout area.
Innovation Solution
A reading method that accelerates the start-up time of word line voltages by initially supplying a higher voltage level than the target voltage, followed by the target voltage level, and utilizing an NMOS transistor for discharging to lower voltage levels during sensing periods, allowing for high-speed read operations without increasing layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sensing time is increased to enable the word line voltage to reach the target voltage level, then reading accuracy is improved, but total read cycle time is increased
Solution Approach 1:
The patent applies preliminary action by pre-charging the word line to a voltage level higher than the target reading voltage before the actual read operation. This preparatory step reduces the time required for the word line voltage to reach the target level during the read cycle, thereby decreasing the sensing time needed while maintaining reading accuracy. The method pre-positions the voltage at an advantageous starting point (higher voltage) to enable faster subsequent operation.
2Productivity
If additional decoders are used to drive the word line voltage to the target voltage faster, then read cycle time is reduced, but layout area is increased
Solution Approach 1:
The patent applies parameter changes by modifying the voltage level parameter of the word line. Instead of adding hardware components, the invention changes the voltage parameter to a higher level during the pre-charge phase, which accelerates the word line voltage establishment without requiring additional decoders. This parameter-based solution achieves faster read speeds while avoiding the layout area increase that would result from adding decoder circuits.
3Reliability
If the word line voltage start-up time is delayed, then the memory performs read operation with insufficient voltage, but increasing sensing time to compensate increases total read cycle
Solution Approach 1:
The patent resolves this contradiction by performing preliminary action - pre-charging the word line to a voltage level higher than the target reading voltage before the read operation begins. This preliminary voltage establishment ensures that when the read operation starts, the word line voltage is already at or near the target level, eliminating the delay problem while keeping the sensing time short. The pre-charge step guarantees voltage reliability without sacrificing speed.
Data Source
AI summary
Reading methods of a nonvolatile semiconductor memory device are described herein. Methods may include supplying, to a word line, one of a voltage corresponding to a highest reading level or a voltage having a level higher than a first reading level of a read operation to be performed on the word line, and subsequently supplying a voltage of the first reading level to the word line and performing the read operation.