Wordline Driver Circuit Power Down Leakage Reduction

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Solution Overview

Problem

Current SRAM circuits experience significant gate leakage during power-down mode, contributing substantially to total power-down leakage, particularly in FinFET-based systems, which is a challenge in optimizing memory leakage for applications like IoT and automotive systems.

Innovation Solution

The introduction of additional switches in the pre-driver stage of the wordline driver circuit, specifically a third switch (SW3) to cut off the gate leakage path and a fourth switch (SW4) to connect wordlines to a different voltage, along with delay circuitry to control switch inputs and prevent glitches during power transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If alternate footer-header switch logic topology is used in wordline driver, then glitch is avoided during power-up, but gate leakage increases significantly during power-down mode

Engineering Contradiction:

Improveglitch avoidance during power-upVSAvoidgate leakage during power-down mode

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The wordline driver circuit is segmented into multiple independent switch-controlled paths. The strap buffer is divided into first and second switches (SW1, SW3) that can be controlled independently, allowing selective disconnection of leakage paths while maintaining glitch-free operation during power-up sequences.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The circuit employs dynamic control of multiple switches (SW1, SW2, SW3, SW4) with different control signals (PD, PD1) to adapt the circuit configuration based on operational mode. During power-down, switches are opened to disconnect leakage paths, while during power-up, the sequence of switch activation prevents glitches.

Inventive Principle:

Principle #15Dynamics

2Loss of energy

If additional switches are added to cut off gate leakage path, then power-down leakage is reduced, but device complexity increases

Engineering Contradiction:

Improvepower-down leakageVSAvoidcircuit complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The additional switches (SW3, SW4) in the strap buffer are designed to serve multiple functions: they act as leakage path disconnection switches during power-down mode and as part of the power-up sequence control to prevent glitches. This multi-functionality reduces the need for separate dedicated components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The invention merges the leakage reduction function with the existing power-up control logic by integrating additional switches into the strap buffer structure. The switches SW1-SW4 work together as a unified control mechanism, combining glitch prevention and leakage reduction in a single circuit architecture rather than adding separate independent systems.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11790982B2Circuits for power down leakage reduction in random-access memory

Publication Date: 2023.10.17 SAMSUNG ELECTRONICS CO LTD

AI summary

The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.