Word Line Switch Layout Under 3D Memory Blocks for Metal Routing
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Solution Overview
Problem
As semiconductor memory devices increase in size, the space required for word line switch transistors and horizontal metal lines becomes a challenge, leading to a shortage of area for all needed metal lines, making it difficult to implement the required connections without increasing the size of the semiconductor die, which is costly and may make the memory physically too large for some applications.
Innovation Solution
The solution involves reducing the size of word line switch transistors and arranging them under blocks of non-volatile memory cells such that groups of X word line switches are positioned in a line under Y blocks, where X>Y, allowing for more efficient use of space and reducing the number of metal lines needed, thereby managing the routing of metal lines more effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If non-volatile memory devices increase in size to accommodate more word lines and memory cells, then the storage capacity is improved, but the area required for word line switch transistors and horizontal metal lines increases, leading to a shortage of area for all needed metal lines
Solution Approach 1:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture. Word line switch transistors are positioned in multiple vertical layers beneath the memory array, with horizontal metal lines routing connections at different elevation levels. This vertical stacking enables more transistors to be accommodated without proportionally increasing the planar footprint, thereby resolving the area shortage for metal lines while maintaining enhanced storage capacity.
2Adaptability or versatility
If more word line switch transistors are positioned at a location horizontally offset from the word line hook up region, then the connectivity is improved, but the number of horizontal metal lines increases, making it difficult to implement all needed connections
Solution Approach 1:
The patent introduces vertical stacking to organize word line switch transistors across multiple layers. Horizontal metal lines are routed at different vertical levels, allowing connections to be made without requiring excessive lateral routing. This multi-layer approach reduces the complexity of horizontal metal line routing while maintaining comprehensive connectivity across the memory array.
Solution Approach 2:
The patent divides the word line switch transistor array into multiple vertical segments or layers. Each layer handles a subset of connections, breaking down the complex routing task into more manageable segments. This segmentation reduces the number of horizontal metal lines required in any single plane while achieving complete connectivity through the stacked architecture.
3Area of stationary object
If the semiconductor die is made larger to accommodate all needed horizontal metal lines, then the area for metal lines is improved, but the costs increase and the memory may become physically too large for some applications
Solution Approach 1:
The patent employs vertical stacking to accommodate all necessary horizontal metal lines within a compact planar footprint. By routing connections at multiple elevation levels rather than spreading them out horizontally, the die size remains small while providing sufficient area for all metal line connections. This approach reduces manufacturing costs and maintains physical compactness suitable for various applications.
Data Source
AI summary
A three dimensional non-volatile memory structure includes word lines connected to non-volatile memory cells arranged in blocks. A plurality of word line switches are connected to the word lines and one or more sources of voltage. The word line switches are arranged in groups of X word line switches such that each group of X word line switches is positioned in a line under Y blocks of non-volatile memory cells and has a length that is equal to the width of the Y blocks of non-volatile memory cells, where X>Y.