Word-line Timing Control for Semiconductor Memory Disturbance Reduction
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Solution Overview
Problem
In semiconductor memory devices, the application of high voltage to word-lines can lead to increased disturbance between memory cells due to reduced gaps between cells, causing interference and data alteration in adjacent cells.
Innovation Solution
A method and device where a selected word-line is enabled in response to a command and subsequently disabled with a negative voltage lower than ground voltage after a reference time interval, corresponding to or greater than the row active time (tRAS) interval, to reduce disturbance on adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the gap between memory cells is reduced to increase storage density, then manufacturing capacity is improved, but disturbance between adjacent cells increases
Solution Approach 1:
The patent applies preliminary anti-action by proactively disabling the selected word-line after a predetermined time interval (tRAS) to prevent disturbance from affecting adjacent memory cells. The control logic circuit monitors the timing and automatically issues a disable command to terminate the high voltage state before it can cause harmful interference to neighboring cells, thus counteracting the disturbance problem that arises from reduced cell spacing.
2Ease of operation
If high voltage is applied to word-line to enable transistor access to memory cell, then access function is improved, but disturbance to adjacent cells increases
Solution Approach 1:
The patent implements periodic action by enabling the word-line with high voltage only for the necessary duration (during the active period triggered by ACT command) and then periodically disabling it after the predetermined time interval tRAS. This time-bound periodic control ensures that the high voltage is applied only when needed for memory access operations, and is terminated promptly to prevent disturbance to adjacent cells, thus balancing access functionality with disturbance reduction.
3Reliability
If word-line is kept enabled for extended period to maintain access capability, then access reliability is improved, but disturbance influence increases
Solution Approach 1:
The patent employs feedback mechanisms through the control logic circuit that monitors the timing of word-line activation and automatically triggers a disable command after the predetermined time interval tRAS. This closed-loop timing control ensures that the word-line remains enabled only for the necessary duration to complete access operations, while providing automatic feedback-based termination to prevent excessive disturbance to adjacent cells, thus maintaining reliability without excessive disturbance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes the influence of disturbance on adjacent word-lines by ensuring timely disablement of the selected word-line, thereby maintaining data integrity and reducing interactions between memory cells.
Implementation Method 1
an electric field that is generated by the high voltage may decrease a threshold voltage of an access transistor in an adjacent cell
Data Source
AI summary
A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.