Wafer-on-Wafer Memory Architecture for Die Alignment and Density
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Solution Overview
Problem
The existing memory device architectures face challenges with misalignment issues due to the size mismatch between peripheral circuitry and memory arrays, leading to inefficient storage density and performance penalties as technology scales down.
Innovation Solution
The wafer-on-wafer (WoW) memory device architecture addresses this by bonding memory array dies with access operation dies using hybrid bonding, allowing for equal or varying sizes, and integrating local media controllers within the access operation dies to reduce I/O traffic and consumption, thereby eliminating size mismatches and enhancing storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory array dies and access operation dies are integrated in traditional architectures, then device functionality is achieved, but size mismatch between peripheral circuitry and memory arrays causes misalignment issues and reduces storage density
Solution Approach 1:
The patent segments the memory device into separate memory array dies and access operation dies that can be independently fabricated and then bonded together. This segmentation allows each component to be optimized independently, eliminating the size mismatch problem that occurs when they are integrated on the same substrate. The memory array dies can be larger than the access operation dies without causing misalignment issues.
Solution Approach 2:
The patent implements a nested structure where access operation dies are bonded onto memory array dies, or vice versa, creating a layered configuration. This nesting approach allows components of different sizes to be combined effectively, with the smaller access operation dies positioned on appropriate regions of the larger memory array dies, maximizing storage density without alignment issues.
2Volume of moving object
If technology scales down to increase storage density, then device size is reduced, but misalignment issues worsen and performance penalties increase
Solution Approach 1:
By segmenting the device into separately fabricated memory array dies and access operation dies, the patent enables independent scaling optimization. Each component can be scaled according to its specific requirements without being constrained by the other, maintaining alignment precision even as overall device size reduces.
Solution Approach 2:
The patent transitions from planar integration to a three-dimensional stacked architecture where memory array dies and access operation dies are bonded in layers. This dimensional change allows for increased storage density within a smaller volume while maintaining proper alignment through the bonding interface.
3Use of energy by moving object
If I/O traffic is reduced to improve energy efficiency, then power consumption decreases, but data access capability may be compromised
Solution Approach 1:
The patent extracts the media controller functionality and places it locally on the memory array die, close to the memory cells. This local placement reduces the distance data must travel, minimizing I/O traffic and power consumption while maintaining full data access capability. The media controller can directly manage memory operations without requiring extensive external communication.
Solution Approach 2:
The patent introduces local media controllers as intermediary components between the memory arrays and external interfaces. These controllers handle data processing and management locally, reducing the volume of data that needs to be transmitted externally and thereby reducing power consumption while preserving data access functionality.
Data Source
AI summary
A memory device includes a memory array die corresponding to a memory array, an access circuitry die corresponding to peripheral circuitry to support access operations with respect to the memory array, and a bonding layer disposed between the memory array die and the access circuitry die to form an interconnection between the memory array and the access circuitry. In some embodiments, the access circuitry die further integrates a local media controller corresponding to the memory array. In some embodiments, the local media controller is located external to the access circuitry die.