Wafer-on-Wafer Stack Segmentation for 3DIC Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing three-dimensional integrated circuits (3DICs) face challenges in yield and cost due to the large size and variability of dies during manufacturing, as well as limited flexibility in functionality and redundancy, which are not effectively addressed by conventional approaches.
Innovation Solution
The implementation of a wafer-on-wafer (WOW) stack configuration where smaller dies of different types are bonded together, with fill materials and parasitic improving regions, allowing for increased yield, reduced production costs, and enhanced functionality through signal re-routing and multiplexing, enabling efficient die replacement and varied functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger dies are used in conventional 3DIC approaches, then fewer dies are needed per wafer, but yield decreases and cost increases due to variability
Solution Approach 1:
The patent divides a large die into multiple smaller dies on the same wafer. Each small die can be independently tested and replaced, increasing yield by allowing faulty small dies to be replaced without discarding the entire large die. The segmentation enables finer-grain redundancy and repair strategies.
Solution Approach 2:
The patent changes the die size parameter from large to small, and alters the die count parameter from fewer to many. This parameter transformation allows the system to achieve higher yield through increased redundancy while maintaining the same functional capacity through parallel operation of multiple small dies.
2Adaptability or versatility
If dies are bonded in a 1:1 ratio with matching sizes, then alignment is simplified, but functionality and redundancy are limited
Solution Approach 1:
The patent makes the first wafer universal by enabling it to work with multiple different second wafers. Each small die on the first wafer can be bonded to corresponding small dies on various second wafers with different functionalities, allowing the system to adapt to different functional requirements without redesigning the first wafer.
Solution Approach 2:
The patent introduces dynamic reconfigurability where the bonding configuration can be changed. Small dies can be selectively bonded to different partners on different wafers, and signal routing can be dynamically adjusted through multiplexing and re-routing, enabling flexible functionality adaptation.
3Reliability
If fill materials are used to fill non-overlapping areas, then mechanical support is provided, but parasitic effects increase
Solution Approach 1:
The patent changes the electrical parameters of the fill material from conductive or semi-conductive to highly resistive. By selecting fill materials with very high resistivity, the parasitic leakage currents are minimized, reducing harmful parasitic effects while maintaining mechanical support function.
Solution Approach 2:
The patent uses simple, inexpensive resistive fill materials that, while providing mechanical support, are intentionally designed to be electrically inert. These fill materials serve their structural purpose without creating significant parasitic effects, effectively disposing of the potential harm rather than trying to eliminate it complexly.
Data Source
AI summary
A wafer on wafer (WOW) stack includes a first wafer having dies of a first type. The WOW stack further includes a second wafer bonded to the first wafer. The second wafer has dies of a second type. An integer number of dies of the second type are bonded to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type. A functionality of the dies of the first type is different from a functionality of the dies of the second type.