Wrap-Around Source/Drain Contacts Using Etch-Selective Cladding
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Solution Overview
Problem
Current semiconductor manufacturing faces challenges in scaling transistors beyond single-digit nanometer nodes due to constraints in three-dimensional integration, particularly in forming wide backside power rails and incorporating signal wiring without increasing parasitic resistances and edge placement errors.
Innovation Solution
A method involving sequential bonding of wafers with epitaxially grown semiconductor layers to form stacked transistors, enabling the creation of wide backside power rails and signal wiring by removing residual FIN structures and using conductive vias to connect power rails to source/drain structures, thereby reducing parasitic resistances and improving interconnect reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional integration is used to increase transistor density, then transistor density is improved, but parasitic resistances increase
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional vertically stacked transistors, allowing multiple transistor tiers to be integrated in the vertical dimension. This enables increased transistor density without proportionally increasing parasitic resistances, as the stacked architecture provides multiple parallel current paths.
Solution Approach 2:
The patent divides the power delivery network into separate tiers corresponding to each transistor stack level. Each tier has its own power rails and interconnect structures, allowing independent optimization and reducing the cumulative parasitic resistance by distributing current paths across multiple segmented levels.
2Use of energy by moving object
If backside power rails are formed to improve power delivery, then power delivery efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms the bonding dielectric layer and bonding interfaces between wafers before forming the backside power rails. This preliminary preparation simplifies subsequent power rail formation by providing pre-defined bonding surfaces and eliminating the need for complex through-wafer etching and filling operations.
Solution Approach 2:
The patent introduces bonding dielectric layers as intermediary materials between wafers and power rail structures. These dielectric layers serve as both bonding agents and isolation materials, simplifying the overall manufacturing process by combining multiple functions into a single material system.
3Length of stationary object
If residual FIN structures are removed to form wide power rails, then power rail width is improved, but manufacturing steps increase
Solution Approach 1:
The patent removes residual FIN structures and forms the bonding dielectric layer before forming the power rails. This preliminary removal of obstacles simplifies the subsequent power rail formation process by providing a clean, flat surface that requires no additional etching or patternning steps.
4Ease of manufacture
If conventional two-dimensional fabrication is used to maintain simplicity, then manufacturing simplicity is preserved, but transistor density remains limited
Solution Approach 1:
The patent extends conventional two-dimensional fabrication processes into the third vertical dimension by stacking multiple transistor tiers. This allows continued use of familiar planar processing techniques while achieving three-dimensional integration and significantly increased transistor density.
Solution Approach 2:
The patent combines multiple wafer-level processing steps into a single integrated three-dimensional structure through wafer bonding. By bonding wafers together with dielectric layers, the patent merges separate two-dimensional transistor layers into a unified three-dimensional device that maintains manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased transistor density and reduced parasitic resistances, enabling more efficient power delivery and signal transmission in semiconductor devices, facilitating further miniaturization and performance enhancement.
Implementation Method 1
bonding a first wafer to a second wafer via a first bonding dielectric layer
Implementation Method 2
a first stack of alternating layers of epitaxially grown semiconductor layers
Implementation Method 3
The second bulk semiconductor material is removed to uncover the first stack
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a stack of epitaxially grown layers alternating between a first semiconductor material and a second semiconductor material that is etch selective to the first semiconductor material. Fin structures are formed from the stack. The fin structures include channel structures formed of the first semiconductor material. Source/drain (S/D) structures are formed on opposing ends of the channel structures by epitaxially growing a third semiconductor material. A silicide is formed around the S/D structures.