Write Assist Circuitry for Memory Bitline RC Delay Reduction
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Solution Overview
Problem
Conventional circuit designs experience voltage drops in signals like bitline signals due to high metal resistance, leading to uneven bitcell write delays and potential write failures, especially at high voltage corners, which limit memory cycle time and increase bitline precharge delay.
Innovation Solution
The implementation of write assist circuitry that drives bitlines from both directions to reduce resistance-capacitance (RC) delay during write operations, using a differential split driver architecture with an equalizer to support write operations on highly resistive bitlines and improve write time and yield under reverse write conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bitline discharge is achieved from one direction (conventional approach), then the circuit design is simpler, but the bitline RC delay increases and write operations fail at high voltage corners
Solution Approach 1:
The bitline discharge operation is segmented into two directional components: a primary discharge path from the bitline driver side and a secondary discharge path from the opposite end through write assist circuitry. This segmentation allows the bitline to be discharged more effectively from both ends simultaneously, reducing the overall RC delay and improving write reliability at high voltage corners without requiring a complete redesign of the entire discharge mechanism
Solution Approach 2:
Write assist circuitry is introduced as an intermediary component at the opposite end of the bitline from the bitline driver. This intermediary circuitry provides an additional discharge path that complements the primary driver-side discharge path, enabling more effective bitline discharge and improving write operation reliability without replacing the original driver architecture
2Productivity
If write assist circuitry is added at both ends of the bitline, then the bitline RC delay is reduced and write time is improved, but the device complexity increases
Solution Approach 1:
Write assist circuitry is selectively implemented only at specific locations (opposite ends of certain bitlines) rather than uniformly across all bitlines. This local application approach optimizes write performance for bitlines that benefit most from dual-ended discharge while minimizing the overall increase in device complexity. The circuitry is strategically placed to address specific RC delay issues without adding unnecessary complexity throughout the entire memory array
Solution Approach 2:
The write assist circuitry provides an additional discharge path that goes beyond the single-directional discharge capability of conventional designs. This partial redundancy (having both driver-side and opposite-end discharge paths) ensures that write operations can complete successfully even when one path is insufficient, thereby improving write speed and reliability without requiring a complete transformation of the discharge architecture
3Area of stationary object
If conventional single-directional bitline discharge is used, then the area is smaller, but the bitcell write delay becomes uneven and cycle time is limited
Solution Approach 1:
The bitline discharge function is segmented into multiple independent discharge paths: one from the bitline driver side and another from the opposite end through write assist circuitry. This segmentation enables parallel discharge action that reduces the overall discharge time and eliminates the uneven write delay experienced in single-directional designs, without requiring a proportional increase in memory array area
Solution Approach 2:
The write assist circuitry is pre-positioned and pre-configured at the opposite end of the bitline, ready to immediately assist the discharge operation when activated. This preliminary preparation ensures that the secondary discharge path is available without delay, enabling faster overall bitline discharge and reducing the cycle time limitation imposed by conventional single-directional discharge approaches
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.