Write Busy Signal Propagation Across Bridge Interfaces
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Solution Overview
Problem
Modern integrated circuit systems face synchronization issues due to long delays in read and write transactions between master and slave devices, which can lead to data being processed out of order or untimely, exacerbated by multiple levels of interface structures and bridge devices.
Innovation Solution
The implementation of dedicated write busy signals on separate write busy bus lines to ensure that master devices are notified when slave devices have accepted write transactions, preventing synchronization issues by asserting and de-asserting these signals in a controlled manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple levels of interface structures and bridge devices are used to increase functionality and connectivity, then the system can support more master and slave devices, but the transaction delays increase and synchronization issues arise
Solution Approach 1:
The patent applies preliminary action by asserting the write busy signal before the write transaction is fully completed and maintaining it asserted until the transaction is complete. This advance signaling prevents master devices from initiating new transactions that could cause synchronization issues, effectively preparing the system for potential delays by controlling transaction timing in advance.
2Productivity
If write transactions are processed quickly without waiting for slave device confirmation, then productivity is improved, but data processing order and accuracy cannot be guaranteed
Solution Approach 1:
The patent implements feedback by using the write busy signal to communicate the status of write transactions from slave devices back to master devices. The signal remains asserted to provide continuous feedback that a write transaction is in progress, allowing master devices to wait appropriately and ensuring data is processed in the correct order without sacrificing overall system productivity.
3Reliability
If write busy signals are asserted only after slave device confirmation, then false busy conditions are reduced, but synchronization issues occur due to delayed notification
Solution Approach 1:
The patent applies preliminary action by asserting the write busy signal in advance, before the write transaction is fully completed by the slave device. This early assertion ensures that master devices are notified promptly and can synchronize their operations accordingly, preventing synchronization issues while maintaining signal accuracy through controlled de-assertion only after confirmation.
Data Source
AI summary
Some examples relate to a method. In the method, a write transaction is routed from a master device to a slave device through a communication path. The communication path includes a first bridge and a second bridge downstream of the first bridge. The first bridge and the second bridge are coupled to one another via an interface structure. The first bridge sets a write busy signal on the communication path when the write transaction is processed by the first bridge; and in response to the first bridge setting the write busy signal, the second bridge holds the write busy signal until the write transaction has been received by the slave device. Upon the slave device receiving the write transaction, the second bridge resets the write busy signal to propagate the reset write busy signal back to the master device through the first bridge.