XOR Logic Gate Using Non-Linear Capacitors to Cut Leakage
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Solution Overview
Problem
Existing multi-input logic gates consume high power due to the large number of transistors and interconnects, which is a challenge for reducing power consumption, especially in battery-powered devices.
Innovation Solution
The use of non-linear polar material-based capacitors in logic gates, specifically in majority or minority gates, which eliminates the need for reset transistors and reduces interconnects, allowing for lower power consumption and more compact designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional multi-input logic gates are used, then logic functionality is achieved, but power consumption increases due to more transistors and interconnects
Solution Approach 1:
The patent changes the fundamental parameter of capacitor linearity to non-linearity. By using non-linear capacitors with specific voltage-dependent capacitance characteristics, the logic gate achieves the same logical functionality with fewer transistors. The non-linear capacitance relationship Q=f(V) creates voltage thresholds that enable logic operations without requiring the full complement of transistors needed in traditional linear capacitor-based designs.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the circuit by using non-linear capacitors with specific localized properties at critical nodes. The non-linear capacitance is concentrated where needed to create voltage thresholds and logic states, rather than uniformly distributing linear capacitance throughout the circuit. This localized application of non-linear properties reduces the overall transistor count while maintaining logic functionality.
2Area of stationary object
If non-linear capacitors are used to reduce power consumption, then area requirements are reduced, but the design complexity increases
Solution Approach 1:
The patent exploits parameter changes in capacitor behavior by using non-linear capacitors whose capacitance varies with voltage. This parameter change enables the same logic functionality to be achieved in a more compact area, as the non-linear capacitance-voltage relationship creates natural voltage thresholds that replace what would otherwise require additional transistors and larger interconnect structures.
Solution Approach 2:
The patent substitutes the mechanical/transistor-based voltage threshold generation with an electrical field-based mechanism using non-linear capacitors. Instead of using multiple transistors to create voltage thresholds through their on/off states, the non-linear capacitor's voltage-dependent capacitance directly creates the threshold effect, reducing the need for additional transistors and interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of non-linear capacitors in logic gates results in lower power consumption, reduced area requirements, and the ability to maintain majority functionality even during periods of inactivity without the need for resets.
Implementation Method 1
non-linear polar material-based capacitors in logic gates
Implementation Method 2
non-linear polar material-based capacitors
Data Source
AI summary
A class of complex logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. At least one input to an individual multi-input majority gate is a fixed input. Other inputs are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node, which provides a majority function of the inputs. The summing node is coupled to a CMOS logic. Leakage through the capacitors is configured such that capacitors of a majority gate have substantially equal leakage, and this leakage has a I-V behavior which is symmetric. As such, reset device(s) on the summing node are not used. The non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels, which reduces the high leakage problem faced from majority gates that use linear input capacitors.