Move Based XOR Optimization for FPGA Logic Array Blocks
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Solution Overview
Problem
Implementing large amorphous systems of combinational logic blocks on integrated circuits, such as FPGAs, is challenging due to the difficulty in finding efficient physical implementations that reduce the number of logic array blocks, leading to increased costs and reduced configurable space.
Innovation Solution
A circuit design component that uses a random move generator and an objective function to determine a metric for each move, searching for a candidate physical implementation that minimizes the number of logic array blocks required, while considering hard and soft constraints, to generate an enhanced circuit design that reduces the number of logic array blocks used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a physical implementation of an amorphous system is selected to implement on an integrated circuit, then the system can be deployed, but the number of logic array blocks used increases leading to higher costs and reduced configurable space
Solution Approach 1:
The patent applies simulated annealing, a dynamic optimization algorithm that iteratively improves the physical implementation by randomly modifying the mapping between logic blocks and circuit resources. The algorithm dynamically adjusts the configuration through controlled random changes, accepting or rejecting modifications based on an objective function that evaluates the number of logic array blocks used, thereby reducing resource consumption while maintaining system functionality
Solution Approach 2:
The patent implements feedback mechanisms where an objective function continuously evaluates each physical implementation configuration and provides metrics on the number of logic array blocks required. This feedback guides the simulated annealing process to iteratively refine the mapping, rejecting configurations that increase resource usage and accepting those that reduce it, thus optimizing the implementation to minimize logic array block consumption
2Quantity of substance
If the number of logic array blocks is reduced to save costs and free space, then cost-savings and configurable space are achieved, but it becomes very difficult to find an efficient physical implementation
Solution Approach 1:
The patent performs preliminary actions by pre-defining the amorphous system logic block structure and constraints before optimization. The simulated annealing algorithm starts with an initial mapping configuration and systematically explores the solution space from this predetermined starting point, allowing the system to methodically reduce logic array blocks while managing complexity through structured exploration rather than random search
Solution Approach 2:
The patent changes parameters by modifying the mapping relationships between logic blocks and circuit resources during the simulated annealing process. The algorithm systematically varies configuration parameters such as the assignment of logic blocks to specific circuit locations and the grouping of functions, using controlled random changes to escape local optima and find configurations that reduce logic array block usage while maintaining system correctness
3Productivity
If random moves are made to search for optimal physical implementation, then the search space can be explored, but the computational complexity increases
Solution Approach 1:
The patent applies partial action by implementing a threshold-based acceptance criterion in the simulated annealing algorithm. Instead of exhaustively evaluating all possible configurations, the algorithm performs a limited number of random moves and accepts modifications that meet certain criteria (such as reducing logic array blocks below a threshold or providing sufficient cost savings). This partial exploration approach reduces computational complexity while still achieving effective optimization by focusing on promising regions of the solution space rather than conducting an exhaustive search
Data Source
AI summary
A computer-implemented method includes receiving a first circuit design comprising a system of XOR gates, iteratively generating a plurality of candidate physical implementations of the system in adaptive logic modules included in logic array blocks of an integrated circuit, determining an overall metric for each of the plurality of candidate physical implementations using an objective function. The overall metric indicates at least an amount of the system that is implemented by each of the candidate physical implementations in a number of moves. The method also includes implementing an enhanced circuit design including a candidate physical implementation based at least in part on the overall metric of the candidate physical implementation on the integrated circuit.