Indirect X-ray Sensor TFT Array Manufacturing Process Integration
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Solution Overview
Problem
The existing manufacturing method for X-ray image TFT arrays involves a complex and time-consuming process with multiple photolithographic and etching steps, leading to increased particle issues and longer manufacturing times, which negatively impact output quantity and quality, especially for indirect X-ray sensors where the storage capacitor area is small, affecting image quality.
Innovation Solution
The method integrates two photolithographic and etching processes into one, simultaneously defining gate lines, lower electrodes, pad electrodes, and common electrodes, and reduces the number of processes for forming through holes, thereby simplifying the process and reducing particle issues, while ensuring the lower and upper electrodes of the storage capacitor have approximately the same size to maintain image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithographic and etching processes are used to manufacture X-ray image TFT arrays, then the manufacturing precision and electrode definition are improved, but the manufacturing time and process complexity increase significantly
Solution Approach 1:
The patent combines multiple photolithographic and etching processes into a single integrated process. Specifically, it forms the gate electrode, lower electrode, upper electrode, and pad electrode simultaneously in one photolithographic step, rather than using separate processes for each electrode. This merging approach maintains the precision of individual electrode formation while dramatically reducing the total manufacturing time and number of process steps.
Solution Approach 2:
The patent employs a universal electrode pattern design where a single photolithographic mask defines multiple electrodes (gate, lower, upper, and pad electrodes) simultaneously. This multi-functional approach allows one process step to perform what previously required multiple separate steps, reducing process complexity while maintaining the ability to precisely define each electrode's position and dimensions.
2Manufacturing precision
If multiple photolithographic and etching processes are used, then the electrode definition is improved, but the device complexity and process steps increase
Solution Approach 1:
The patent merges the formation of gate electrodes, lower electrodes, upper electrodes, and pad electrodes into a single photolithographic and etching process. This consolidation reduces process complexity by eliminating multiple sequential steps while maintaining precise electrode definition through a carefully designed unified pattern transfer process.
Solution Approach 2:
While combining processes, the patent uses segmentation in the electrode design to distinguish different electrode functions within the unified structure. The gate electrode, lower electrode, upper electrode, and pad electrode are defined as separate conductive regions with distinct functions, allowing precise control of each electrode's geometry and position even though they are formed in a single process step.
3Manufacturing precision
If the storage capacitor area is reduced for indirect X-ray sensors, then the image quality is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by optimizing the electrode dimensions specifically for the storage capacitor region. The lower electrode and upper electrode are designed with controlled areas that are smaller than conventional designs, locally adapting the electrode size to match the reduced storage capacitor area requirements for indirect X-ray sensors. This localized optimization maintains precise manufacturing control while reducing overall capacitor size.
Data Source
AI summary
The present invention discloses a method of manufacturing an image TFT array and a structure thereof. A substrate is provided. At least one first line, a lower electrode, a pad electrode, a common electrode and a first electrode connected with the first line are defined simultaneously by etching a first conductive layer. At least one second line intersecting the first line, an upper electrode corresponding to the lower electrode, a second electrode connected with the second line and a third electrode connected with the upper electrode are defined simultaneously by etching a second conductive layer applied to cover the substrate and above the first conductive layer.