X-Tolerant Scan Compression Using Segmented MISRs
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Solution Overview
Problem
Current scan testing methods for integrated circuits face inefficiencies due to high test pattern volumes, increased tester time, and the challenge of handling uncertain bits (X bits) that limit compression and observability, especially in complex and aggressive designs.
Innovation Solution
A scan test system utilizing two pseudo-random pattern generator (PRPG) processing chains and an unload block with X-tolerant control bits to provide per-shift X-control, allowing for high compression and observability while adapting to varying X densities, using a method that maps care and X-tolerant control bits to seeds for efficient pattern generation and analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scan compression techniques are used to reduce test pattern volume, then test cost and tester pin count requirements are reduced, but the presence of uncertain bits (X bits) limits compression effectiveness and observability
Solution Approach 1:
The patent segments the scan chain outputs into multiple groups, with each group fed to a separate MISR (Multiple Input Shift Register). This segmentation allows independent handling of X bits in different groups, preventing X bits in one group from corrupting the analysis of other groups, thereby maintaining observability while enabling compression.
Solution Approach 2:
The patent introduces MISRs as intermediary components between the scan chains and the test response analysis. These MISRs act as mediators that can tolerate X bits by using multiple inputs to mask out uncertain bits, allowing compressed test patterns to be applied while maintaining reliable fault detection capability.
2Reliability
If deterministic ATPG is used to generate test patterns with fault coverage close to 100%, then fault coverage is improved, but significant storage area in tester and off-chip access time are required
Solution Approach 1:
The patent performs preliminary action by pre-configuring the scan chains and MISRs with appropriate seed values before test pattern application. This allows the system to generate deterministic test patterns with high fault coverage through on-chip PRPGs, eliminating the need for extensive off-chip storage and access time while maintaining near-100% fault coverage.
3Productivity
If built-in self-test (BIST) structures with pseudorandom pattern generators are used, then test cost is reduced and testing speed is improved, but fault coverage is lower compared to deterministic ATPG
Solution Approach 1:
The patent implements a dynamic system that can switch between different test modes and configurations. The MISRs can dynamically adjust their configuration to optimize between fault coverage and testing speed, allowing the system to achieve both high productivity and reliable fault detection by adapting to the specific test requirements.
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AI summary
Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.