Zener Diode Anode Doping Layout for Parasitic Thyristor Suppression
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Solution Overview
Problem
Semiconductor devices with Zener diodes face performance limitations due to the operation of parasitic thyristors, which degrade device performance and are difficult to suppress without compromising withstand voltage control.
Innovation Solution
The semiconductor device design includes a p-type anode region with a higher impurity concentration under the n-type cathode region, forming a PN junction that sets the withstand voltage and suppresses parasitic thyristor operation by adjusting the impurity concentration through ion implantation, while minimizing planar dimensions for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the anode region is increased to suppress parasitic thyristor operation, then device reliability improves, but the withstand voltage control becomes difficult
Solution Approach 1:
The anode region is segmented into multiple semiconductor layers with different impurity concentrations. The first semiconductor layer has a first impurity concentration while the second semiconductor layer has a second impurity concentration that is different from the first. This segmentation allows different portions of the anode region to serve different functions: one portion suppresses parasitic thyristor operation while another portion maintains proper withstand voltage characteristics.
Solution Approach 2:
Different local regions of the anode region are assigned different impurity concentrations to optimize local performance. The first semiconductor layer and second semiconductor layer have distinct impurity concentrations tailored to their specific functional requirements within the overall anode structure, allowing simultaneous achievement of parasitic suppression and voltage control.
2Productivity
If the semiconductor device is miniaturized by reducing planar dimensions, then productivity improves, but parasitic thyristor operation becomes more likely
Solution Approach 1:
The solution moves from two-dimensional planar scaling to three-dimensional structural optimization. Instead of simply reducing the planar area of the anode region, the invention creates a multi-layered vertical structure with different impurity concentrations at different depths. This dimensional transition allows parasitic suppression functionality to be achieved through vertical layering rather than horizontal spacing, enabling miniaturization without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses parasitic thyristor operation, improves semiconductor device performance, and maintains reliable withstand voltage, enabling miniaturization and enhanced reliability of Zener diode-based semiconductor devices.
Implementation Method 1
adjusting the impurity concentration through ion implantation
Data Source
AI summary
A semiconductor substrate includes a p-type substrate body, an n-type buried layer on the p-type substrate body, and a p-type semiconductor layer on the n-type buried layer. A DTI region penetrates through the p-type semiconductor layer and the n-type buried layer, and reaches the p-type substrate body. An n-type semiconductor region, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer. The p-type anode region includes a p-type first semiconductor region formed under the n-type semiconductor region, and a p-type second semiconductor region formed under the p-type first semiconductor region. A PN junction is formed between the p-type first semiconductor region and the n-type semiconductor region. An impurity concentration of the p-type second semiconductor region is higher than an impurity concentration of the p-type first semiconductor region.