Zero-Copy Data Sharing Asymmetric Coprocessors

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Solution Overview

Problem

Conventional parallel processing systems incur inefficiencies due to the need for data copying between CPU and PPU memory, leading to increased processing latency and memory bandwidth issues.

Innovation Solution

Implementing a shared memory configuration that allows asymmetric coprocessors to access and share a portion of physical memory, reducing the need for data copying between CPU and PPU by allocating a portion as shared memory and another as private memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is copied between CPU and PPU memory, then data can be processed by both processors, but processing latency increases and memory bandwidth is consumed

Engineering Contradiction:

Improvedata processing throughputVSAvoidprocessing latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent merges CPU memory and PPU memory into a unified memory space where both processors can access the same physical memory locations. This eliminates the need for data copying between separate memory spaces, allowing both CPUs and PPU threads to directly access and process the same data simultaneously, thereby reducing latency while maintaining processing throughput.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If data is copied between CPU and PPU memory, then data can be accessed by both processors, but memory bandwidth is consumed

Engineering Contradiction:

Improvedata processing throughputVSAvoidmemory bandwidth consumption

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

By combining CPU and PPU memory access into a single unified memory space, the patent eliminates redundant data transfers. Both processors read from and write to the same physical memory locations, preventing duplicate data movement and conserving memory bandwidth that would otherwise be consumed by copy operations.

Inventive Principle:

Principle #5Merging (Combining)

3Ease of manufacture

If separate memory spaces are used for CPU and PPU, then memory allocation is simple, but data sharing requires copying

Engineering Contradiction:

Improvememory allocation simplicityVSAvoiddata sharing efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent merges previously separate CPU and PPU memory spaces into a unified memory architecture. This allows data to be shared directly between processors without copying, significantly improving data sharing efficiency while maintaining straightforward memory allocation through a single unified address space.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8645634B1Zero-copy data sharing by cooperating asymmetric coprocessors

Publication Date: 2014.02.04 NVIDIA CORP

AI summary

One embodiment of the present invention sets forth a technique for reducing the copying of data between memory allocated to a primary processor and a coprocessor is disclosed. The system memory is aliased as device memory to allow the coprocessor and the primary processor to share the same portion of memory. Either device may write and/or read the shared portion of memory to transfer data between the devices rather than copying data from a portion of memory that is only accessible by one device to a different portion of memory that is only accessible by the other device. Removal of the need for explicit primary processor memory to coprocessor memory and coprocessor memory to primary processor memory copies improves the performance of the application and reduces physical memory requirements for the application since one portion of memory is shared rather than allocating separate private portions of memory.