Zero Diffusion Break Layout With Wrap-Around Contacts
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of multi-gate transistors to sub-10 nanometer nodes, leading to challenges in contact resistance and layout constraints, particularly with zero diffusion break structures.
Innovation Solution
The implementation of zero diffusion break with wrap-around contacts and backside power delivery, along with differentiated backside access features, to enhance contact resistance and reduce layout area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistors, then manufacturing compatibility and cost are maintained, but manufacturing precision and scalability to sub-10 nanometer nodes deteriorate due to process variability
Solution Approach 1:
The fabrication process is divided into separate stages: forming the gate structure first, then adding diffusion breaks afterward. This segmentation allows each stage to be optimized independently, enabling sub-10 nanometer precision without requiring the entire process to meet the most stringent constraints simultaneously
Solution Approach 2:
The gate structure is formed in advance before the diffusion regions are defined. This preliminary action establishes a reference framework that guides subsequent diffusion break placement, improving alignment precision and reducing variability in the final device dimensions
2Area of stationary object
If zero diffusion break structures are implemented, then layout area is reduced, but contact resistance increases due to process variability
Solution Approach 1:
The diffusion region is segmented by inserting diffusion breaks between adjacent active diffusion areas. This segmentation isolates each contact region, preventing process variability from affecting neighboring contacts and thereby reducing contact resistance while maintaining compact layout
Solution Approach 2:
Diffusion breaks are selectively placed only where needed between specific diffusion regions rather than uniformly across the entire structure. This local application maintains low contact resistance at critical interfaces while still achieving layout area reduction
3Quantity of substance
If transistor dimensions are scaled down to increase density, then capacity increases, but process constraints become overwhelming and manufacturing precision deteriorates
Solution Approach 1:
By segmenting the diffusion process into discrete regions separated by diffusion breaks, the patent enables independent control and optimization of each diffusion zone. This segmentation allows precise doping profiles even at reduced transistor dimensions, maintaining manufacturing precision while increasing density
Solution Approach 2:
The patent introduces diffusion breaks as a vertical/dimensional feature within the planar layout, adding a new dimension of control without increasing the footprint. This allows higher transistor density while maintaining process control through the additional structural element
Data Source
Figure 1A(a)~1A(c)
Figure 1B
Figure 2A~2B
AI summary
Integrated circuit structures having zero diffusion break and wrap-around contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure having a cut extending there through to separate a first portion of the epitaxial source or drain structure from a second portion of the epitaxial source or drain structure.