2D Zero-Line Interconnect Layout for Higher IC Density
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Solution Overview
Problem
Existing integrated circuit (IC) fabrication methods face challenges in efficiently forming interconnects with zero line end extensions, leading to increased space requirements and reduced density of device placement.
Innovation Solution
The implementation of self-aligned via formation techniques, including merging vias with dummy lines and etching to create trenches, allows for the formation of interconnects with zero line extensions in two dimensions, enabling a denser layout by eliminating unnecessary metal line extensions beyond via edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal lines are extended beyond via edges for robust connections, then connection reliability is improved, but space efficiency deteriorates and interconnect density is reduced
Solution Approach 1:
The patent transitions from traditional one-dimensional metal line extensions beyond via edges to a two-dimensional L-shaped layout where metal lines meet exactly at via edges. This dimensional reconfiguration eliminates redundant extensions while maintaining connection robustness through precise alignment, thereby improving space efficiency without sacrificing reliability
2Reliability
If metal lines are extended beyond via edges, then connection robustness is improved, but device density deteriorates
Solution Approach 1:
The invention adopts an L-shaped layout configuration that repositions metal lines to meet precisely at via edges in a two-dimensional arrangement. This eliminates the need for extended metal lines while maintaining robust connections, thereby increasing the number of devices that can be closely connected per unit area and improving overall device density
Solution Approach 2:
The patent modifies the geometric parameters of the interconnect layout by changing from extended linear configurations to compact L-shaped configurations. This parameter change reduces the space occupied by each interconnect while maintaining connection robustness, enabling higher device density
3Area of stationary object
If zero line extension layout is implemented, then space efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning steps that pre-establish the positions of metal lines and vias before final assembly. This preliminary action ensures that when metal lines are configured in L-shaped layouts with zero extensions, they are pre-aligned to meet precisely at via edges, thereby reducing the actual manufacturing precision demands during final fabrication
Data Source
AI summary
Embodiments of the invention include providing interconnects with two-dimensional free zero line end enclosure. A first metal line is formed. A second metal line is connected by a via to the first metal line, the first metal line having a first end with a zero line extension in relation to the via in a first dimension, the second metal line having another first end with a zero line extension in relation to the via in a second dimension perpendicular to the first dimension.