Self-Aligned Zero-Via Layer for ReRAM Interconnects
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Solution Overview
Problem
Conventional methods face challenges in forming reliable connections between multiple layers of an integrated circuit within small surface areas, particularly in resistive random access memory (ReRAM) technology, due to difficulties in spacing and design constraints for forming vias in photoresist.
Innovation Solution
The implementation of a self-aligned zero-via layer with conductors that are aligned with the overlying metal level, allowing for the formation of via conductors orthogonal to each other, enabling reliable connections between transistor source/drain regions and resistive memory elements without the need for traditional vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional vias are formed to connect transistor source/drain to resistive memory elements, then reliable connections are achieved, but it becomes increasingly difficult to form openings with sufficient spacing from other openings as mask sizes shrink
Solution Approach 1:
The patent introduces a zero-via layer positioned between the device layer and first metal level, creating an additional dimensional plane for interconnect formation. This zero-via layer contains via conductors that extend vertically to contact source/drain regions, while metal level patterns in the first metal level self-align with these via conductors. This dimensional addition allows connections to be formed without traditional vias in the conventional sense, thereby achieving sufficient spacing while maintaining connection reliability.
Solution Approach 2:
The patent implements self-alignment where metal level patterns in the first metal level automatically align with via conductors in the zero-via layer through a single patterning process. This self-alignment mechanism eliminates the need for separate alignment steps and reduces manufacturing complexity, allowing the structure to self-organize the connections without requiring precise manual positioning of vias.
2Area of stationary object
If mask sizes are reduced to achieve smaller surface areas, then integration density is improved, but it becomes increasingly difficult to form openings for vias with sufficient spacing from other openings
Solution Approach 1:
By introducing the zero-via layer as an intermediate plane, the patent enables via conductors to be formed at a different vertical level than traditional vias. This allows the via conductors to be positioned such that they connect to source/drain regions while maintaining sufficient horizontal spacing from other structures, thereby achieving small surface area without compromising manufacturability.
Solution Approach 2:
The self-alignment mechanism between metal level patterns and via conductors simplifies the manufacturing process by eliminating complex alignment steps. This self-service approach allows for easier formation of connections even as mask sizes are reduced, maintaining ease of manufacture while achieving higher integration density.
3Adaptability or versatility
If traditional vias are used to connect multiple layers, then inter-layer connections are established, but the complexity of via formation increases with shrinking dimensions
Solution Approach 1:
The patent extracts the via formation step from the traditional multi-layer interconnect process by introducing a dedicated zero-via layer. This separation allows via conductors to be formed independently with simplified geometry, reducing the complexity of via formation while maintaining the essential inter-layer connection capability between the device layer and first metal level.
Solution Approach 2:
The self-alignment mechanism automatically positions metal level patterns relative to via conductors, eliminating the need for complex alignment procedures. This self-service approach reduces device complexity by allowing the structure to self-organize connections without requiring sophisticated formation processes.
Data Source
AI summary
The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.