Zigzag Bit Line Layout for Higher-Density DRAM Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The tetragonal structure in 4F2 DRAM with vertical transistors results in suboptimal area efficiency for storage capacitors, leading to significant waste of area and reduced memory density.
Innovation Solution
Implementing a hexagonal close-packed arrangement by forming bit lines in a zigzag shape and adjusting their intersection angle with word lines to 60 degrees, reducing the proportion of useless area and enhancing memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a tetragonal structure with vertical transistors is used, then the manufacturing process is simplified, but the area efficiency for storage capacitors is reduced
Solution Approach 1:
The patent transforms the symmetric tetragonal structure into an asymmetric hexagonal close-packed structure by arranging bit lines and word lines at 60-degree angles. This asymmetric arrangement optimizes the spatial distribution of storage capacitors, achieving higher area efficiency while maintaining manufacturing feasibility through the zigzag bit line configuration
Solution Approach 2:
The patent introduces a zigzag dimension to the bit lines, transforming straight linear paths into multi-segment zigzag paths. This dimensional change allows the bit lines to intersect word lines at optimal angles while maintaining connectivity, enabling the hexagonal close-packed arrangement that improves area efficiency
2Device complexity
If bit lines and word lines intersect at right angles in a tetragonal structure, then the layout is simple, but useless intersection area increases
Solution Approach 1:
The patent replaces the symmetric right-angle intersection with asymmetric 60-degree angle intersections between bit lines and word lines. This asymmetric configuration eliminates redundant intersection areas by optimizing the spatial relationship between conductive lines, reducing useless area while maintaining layout manageability through the systematic zigzag pattern
Solution Approach 2:
The zigzag bit line configuration serves multiple functions simultaneously: it creates optimal 60-degree intersection angles with word lines, enables hexagonal close-packed transistor arrangement, reduces useless intersection area, and maintains electrical connectivity. This multi-functional design achieves area optimization without proportionally increasing layout complexity
Data Source
AI summary
A method for manufacturing a semiconductor structure includes: a substrate; and a plurality of parallel word lines and a plurality of parallel bit lines on the substrate. For each bit line, the bit line is in a zigzag shape, each two adjacent segments among segments of the bit line with the zigzag shape form a first angle, the bit line has at least one first angle, and the bit line intersects the word lines to form a second angle.