Zigzag Body Wiring for NAND Flash Parasitic Capacitance
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Solution Overview
Problem
The scaling of NAND flash memory devices leads to increased parasitic capacitance between word and bit lines, causing delays and limiting the development of memory controllers, as the distance between lines decreases and the number of lines per unit space increases, resulting in notable word and bit line delays.
Innovation Solution
The implementation of zigzag body wiring for both word and bit lines, where the lines are arranged alternately at higher and lower planes with varying inter-poly dielectric film thicknesses, reduces parasitic capacitance by increasing the distance between neighboring lines, and the use of specific voltage equations ensures uniform self-potentials across the memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between neighboring bit lines is reduced to increase the number of bit lines per unit space, then the storage density is improved, but the parasitic capacitance between bit lines increases causing bit line delay
Solution Approach 1:
The patent applies self-align shallow trench isolation (SA-STI) that extends vertically into the substrate, creating isolation structures at different depths. This three-dimensional isolation approach separates bit lines at different vertical levels while maintaining horizontal proximity, thereby increasing storage density without proportionally increasing parasitic capacitance between adjacent bit lines.
Solution Approach 2:
The patent introduces shallow trench isolation structures as intermediary elements between neighboring bit lines. These isolation trenches filled with dielectric material act as mediators that reduce the electric field coupling between adjacent bit lines, thereby reducing parasitic capacitance while allowing the bit lines to remain closely spaced for high density.
2Productivity
If the distance between neighboring word lines is reduced to increase the number of word lines per unit space, then the storage density is improved, but the parasitic capacitance between word lines increases causing word line delay
Solution Approach 1:
The patent employs SA-STI structures that extend vertically to isolate word lines at different depths. This vertical dimensionality allows word lines to be closely spaced horizontally for high density while being separated vertically by isolation structures, reducing parasitic capacitance between adjacent word lines.
Solution Approach 2:
Shallow trench isolation structures serve as intermediary elements between neighboring word lines, reducing electric field coupling and parasitic capacitance. The dielectric-filled trenches act as mediators that enable close horizontal spacing while maintaining electrical isolation.
3Productivity
If the cell-to-cell space is shrunk to reduce bit cost through miniaturization, then the storage density is improved, but the parasitic capacitance between neighboring word lines increases causing word line delay
Solution Approach 1:
The patent uses vertically extending shallow trench isolation structures to maintain electrical separation between miniaturized cells. As cell dimensions are reduced in the horizontal plane, the vertical isolation structures prevent proportional increases in parasitic capacitance by providing three-dimensional separation between adjacent word lines and cells.
Data Source
AI summary
Provided is a fabrication method of a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are formed on a substrate, wherein the first word lines and the second word lines are arranged periodically and extend in a first direction. Bit lines are formed over the first and second word lines, wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word lines to the substrate.