Etch Control Layer for Precise Isolation in Semiconductor Devices
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Summary
Problems
The challenge in semiconductor manufacturing is controlling the etch depth of isolation trenches during the cut-metal-gate (CMG) process, which can damage the substrate and induce current leakage paths between finFETs.
Innovation solutions
The introduction of an etch control layer with a lower etch selectivity than the gate structures prevents isolation trenches from extending into the substrate, allowing for precise control of etch depth and reducing the risk of substrate damage and current leakage.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the etch depth of isolation trenches is increased to fully isolate gate structures, then isolation effectiveness is improved, but substrate damage and current leakage paths are induced
Why choose this principle:
A new etch control layer is introduced as an intermediary between the substrate and gate structures. This layer acts as a mediator that stops the etching process before it reaches the substrate, preventing substrate damage while still achieving complete isolation of the gate structures. The etch control layer is specifically designed with etch selectivity that allows it to be etched faster than the gate structures, enabling precise depth control.
Principle concept:
If the etch depth of isolation trenches is increased to fully isolate gate structures, then isolation effectiveness is improved, but substrate damage and current leakage paths are induced
Why choose this principle:
The etch control layer is formed in advance before the isolation trench etching process. By pre-positioning this layer at the desired etch stop depth, the system prepares a predetermined barrier that automatically limits the etch depth during subsequent processing, eliminating the need for complex real-time depth control while preventing substrate damage.
Application Domain
Data Source
AI summary:
The introduction of an etch control layer with a lower etch selectivity than the gate structures prevents isolation trenches from extending into the substrate, allowing for precise control of etch depth and reducing the risk of substrate damage and current leakage.
Abstract
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a fin structure having a first fin portion and a second fin portion, forming a first dielectric layer on the substrate and on sidewalls of the first fin portion, forming a second dielectric layer on the first dielectric layer, performing an oxidation process on the second fin portion to form an oxide layer, depositing a gate dielectric layer on the oxide layer and on the second dielectric layer, depositing a gate conductive layer on the gate dielectric layer, and forming an isolation structure extending through the gate conductive layer, the gate dielectric layer, and the second dielectric layer.