Stress-Balanced Power Module Design for Enhanced Reliability
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Summary
Problems
Existing surface-mount power semiconductor packages face reliability issues due to thermo-mechanical stresses caused by varying thermal expansion coefficients of constituent materials, leading to package warpage and compromised second-level interconnections.
Innovation solutions
A surface-mount package structure with a stress balance-based design, featuring a multi-layer substrate with direct bond copper layers and a dielectric filler material to reduce thermal and bending stresses, along with second-level solder bumps for robust interconnections.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If dielectric organic material and ceramic substrate are used in POL package, then electrical and thermal connectivity is achieved, but varying CTEs cause thermal and bending stresses leading to package warpage
Why choose this principle:
The patent applies asymmetry by implementing a stress balance design where the ceramic substrate has an asymmetric multi-layer structure with different metal layer configurations on each side. The first metal layer is coupled to the dielectric organic material while the second metal layer is positioned on the opposite side, creating an asymmetric stress distribution that counteracts thermal expansion differences and prevents package warpage during thermal cycling
Principle concept:
If dielectric organic material and ceramic substrate are used in POL package, then electrical and thermal connectivity is achieved, but varying CTEs cause thermal and bending stresses leading to package warpage
Why choose this principle:
The patent employs parameter changes by carefully controlling the thickness, material composition, and thermal expansion coefficients of each layer in the multi-layer ceramic substrate. By adjusting these parameters, the overall CTE of the substrate is optimized to match the dielectric organic material, reducing thermal stresses and maintaining package flatness across temperature variations
Application Domain
Data Source
AI summary:
A surface-mount package structure with a stress balance-based design, featuring a multi-layer substrate with direct bond copper layers and a dielectric filler material to reduce thermal and bending stresses, along with second-level solder bumps for robust interconnections.
Abstract
A surface mount packaging structure that yields improved thermo-mechanical reliability and more robust second-level package interconnections is disclosed. The surface mount packaging structure includes a sub-module having a dielectric layer, semiconductor devices attached to the dielectric layer, a first level metal interconnect structure electrically coupled to the semiconductor devices, and a second level I/O connection electrically coupled to the first level interconnect and formed on the dielectric layer on a side opposite the semiconductor devices, with the second level I/O connection configured to connect the sub-module to an external circuit. The semiconductor devices of the sub-module are attached to the first surface of a multi-layer substrate structure, with a dielectric material positioned between the dielectric layer and the multi-layer substrate structure to fill in gaps in the surface-mount structure and provide additional structural integrity thereto.