Low-Capacitance LDMOS Design for High Switching Frequency
Here’s PatSnap Eureka !
Summary
Problems
Traditional LDMOS devices face challenges in achieving low on-resistance and high switching frequency, particularly at higher voltages, due to increased input capacitance and hot carrier effects, which limit their performance in applications like fast charging and high-voltage grade devices.
Innovation solutions
The design features a polysilicon field plate connected to the source over the drift region, with additional doping on the surface below the polysilicon field plate, and the body region boundary flush or exceeding the polysilicon gate, reducing input capacitance and shielding the polysilicon gate's influence on the drift region to enhance switching frequency and robustness against hot carriers.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If polysilicon gate covers part of the drift region to form an accumulation region, then on-resistance is reduced, but input capacitance increases and switching frequency decreases
Why choose this principle:
The invention segments the gate structure into two parts: a polysilicon gate and a polysilicon field plate. The polysilicon gate forms an accumulation region to reduce on-resistance, while the polysilicon field plate extends over the drift region to shield the gate-drain capacitance. This segmentation allows the device to achieve low on-resistance without the penalty of high input capacitance, thereby maintaining high switching frequency.
Principle concept:
If polysilicon field plate is introduced over the drift region, then Cgd is reduced and hot carrier robustness is improved, but on-resistance increases
Why choose this principle:
The invention applies local quality by introducing additional doping on the surface of the drift region below the polysilicon field plate. This creates a localized accumulation region with high carrier concentration directly beneath the field plate, compensating for the increased on-resistance caused by the field plate structure. The local doping ensures that the current path maintains low resistance while the field plate continues to provide shielding and improve hot carrier robustness.
Application Domain
Data Source
AI summary:
The design features a polysilicon field plate connected to the source over the drift region, with additional doping on the surface below the polysilicon field plate, and the body region boundary flush or exceeding the polysilicon gate, reducing input capacitance and shielding the polysilicon gate's influence on the drift region to enhance switching frequency and robustness against hot carriers.
Abstract
A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein C gd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating C gd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.