Multi-Level Voltage Sensing Circuit for Accurate DRAM Operations
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Summary
Problems
Multi-level DRAMs face challenges in accurately detecting changes in bit line voltages due to reduced voltage differences between reference and neighboring voltages, as well as the impact of temperature and noise.
Innovation solutions
A circuit for sensing multi-level voltages of a bit line is designed for multi-bit operations in DRAM, comprising a bit line connected to a memory cell, an operational amplifier, a feedback capacitor, and an analogue-to-digital converter, which enables precise detection of cell voltages despite temperature and noise variations.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a sense amplifier is used to read data in multi-level DRAM, then data can be read from the memory cell, but the voltage difference between reference voltage and neighboring reference voltages becomes smaller making it difficult to accurately detect bit line voltage changes
Why choose this principle:
The patent segments the voltage detection process into multiple stages: pre-charging stage, sensing stage, and amplification stage. The sense amplifier is divided into multiple sub-amplifiers that independently process different voltage levels, allowing each segment to optimize for its specific function and improve overall detection precision.
Principle concept:
If a sense amplifier is used to read data in multi-level DRAM, then data can be read from the memory cell, but the voltage difference between reference voltage and neighboring reference voltages becomes smaller making it difficult to accurately detect bit line voltage changes
Why choose this principle:
The patent introduces intermediate voltage reference lines and buffer circuits between the bit line and the sense amplifier. These intermediary elements condition the voltage signals before they reach the amplification stage, enhancing the detectability of small voltage differences caused by multi-level charge sharing.
Application Domain
Data Source
AI summary:
A circuit for sensing multi-level voltages of a bit line is designed for multi-bit operations in DRAM, comprising a bit line connected to a memory cell, an operational amplifier, a feedback capacitor, and an analogue-to-digital converter, which enables precise detection of cell voltages despite temperature and noise variations.
Abstract
The present invention relates to a bitline multi-level voltage sensing circuit for a multi-bit operation of a DRAM including a memory cell that stores data by an operation of a wordline and a bitline, the bitline multi-level voltage sensing circuit comprising: an operational amplifier having a non-inverting input terminal coupled to a precharging voltage line and an inverting input terminal coupled to a bitline through a first switch enabled by a wordline signal; a feedback capacitor formed between an output terminal of the operational amplifier and an inverting input terminal of the operational amplifier; a second switch formed in parallel with the feedback capacitor between the output terminal of the operational amplifier and the inverting input terminal of the operational amplifier and enabled by a precharging signal; and an analog-to-digital converter that converts an output voltage of the output terminal of the operational amplifier into a digital signal.