High-Speed PCB Soldered Interface for Crosstalk Reduction
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Summary
Problems
Conventional VPX connectors face challenges in supporting 25 Gbps data rates with Bit Error Rates (BER) of 1E−15 or better due to crosstalk issues in the via field, limiting their performance in high-speed communication applications, especially in avionics and military environments.
Innovation solutions
The implementation of a novel connector and Printed Wiring Board (PWB) structure using Double Transition (DT) vias and a soldered interface with a stacked arrangement of solder, where the connector pin is soldered into a blind via with a buried via configuration, reducing cross talk by minimizing parasitic capacitance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If conventional VPX connectors are used, then structural simplicity is maintained, but crosstalk increases at 25 Gbps data rates
Why choose this principle:
The via structure is segmented into multiple types (blind vias, buried vias, micro-vias) with different functions and positions. Blind vias are used for connector pins to reduce parasitic capacitance, buried vias are offset from signal vias to reduce crosstalk, and micro-vias connect different layers. This segmentation allows each via type to be optimized for its specific function, reducing overall crosstalk while managing complexity.
Principle concept:
If conventional VPX connectors are used, then structural simplicity is maintained, but crosstalk increases at 25 Gbps data rates
Why choose this principle:
Different via structures are applied to different locations based on their specific requirements. Signal vias have specific diameter and depth requirements, blind vias are positioned at specific depths to minimize parasitic capacitance, and buried vias are offset from signal paths. This localized optimization reduces crosstalk in critical areas while maintaining overall structural efficiency.
Application Domain
Data Source
AI summary:
The implementation of a novel connector and Printed Wiring Board (PWB) structure using Double Transition (DT) vias and a soldered interface with a stacked arrangement of solder, where the connector pin is soldered into a blind via with a buried via configuration, reducing cross talk by minimizing parasitic capacitance.
Abstract
Systems and methods for providing a soldered interface between a circuit board and a connector pin. The methods comprise: using a jet paste dispenser to apply first solder into a plated contact cavity formed in the circuit board; using a stencil screen printer to apply second solder (a) over the plated contact cavity which was at least partially filled with the first solder by the jet paste dispenser and (b) over at least a portion of a pad surrounding the plated contact cavity; inserting the connector pin in the plated contact cavity such that the connector pin passes through the second solder and extends at least partially through the first solder; and performing a reflow process to heat the first and second solder so as to create a solder joint between the circuit board and the connector pin.