Semiconductor Memory Design Without Capacitors for Higher Density
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Summary
Problems
Conventional semiconductor memory devices face challenges in maintaining high cell density as the size of memory cells decreases, particularly due to the large physical space occupied by capacitors in DRAM devices, which hinders further integration and efficiency.
Innovation solutions
The semiconductor device integrates read and write transistors electrically connected over a substrate, utilizing a read gate dielectric layer as a storage dielectric and a read gate electrode as a storage electrode, allowing for voltage-level storage and retention without a capacitor, enhancing memory cell density and performance.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If a capacitor is used in the memory cell structure, then signal storage and retention is achieved, but the physical space occupied increases, reducing memory cell density
Why choose this principle:
The patent extracts and eliminates the capacitor component from the traditional 1T-1C memory cell structure. Instead of using a separate capacitor for charge storage, the invention utilizes the gate dielectric layer of the read transistor itself as the storage medium, thereby removing the space-occupying capacitor while maintaining signal retention capability
Principle concept:
If a capacitor is used in the memory cell structure, then signal storage and retention is achieved, but the physical space occupied increases, reducing memory cell density
Why choose this principle:
The read gate dielectric layer serves multiple functions simultaneously: it acts as the gate insulator for the read transistor and as the charge storage medium traditionally provided by a capacitor. This multi-functionality eliminates the need for a separate capacitor component, reducing memory cell area while maintaining signal storage capability
Application Domain
Data Source
AI summary:
The semiconductor device integrates read and write transistors electrically connected over a substrate, utilizing a read gate dielectric layer as a storage dielectric and a read gate electrode as a storage electrode, allowing for voltage-level storage and retention without a capacitor, enhancing memory cell density and performance.
Abstract
A semiconductor device according to an embodiment of the present disclosure includes a read transistor and a write transistor that are electrically connected to each other over a substrate. The read transistor includes a read channel layer disposed on a plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer. The write transistor includes a write channel layer disposed over a portion of the read gate electrode layer, a write bit line disposed on an upper surface of the write channel layer, a write gate dielectric layer on a side surface of the write channel layer, and a write word line disposed to be adjacent to the write gate dielectric layer.