Semiconductor Packaging for Enhanced Thermal Dissipation
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Summary
Problems
The integration of multiple semiconductor devices in miniaturized electronic apparatus poses challenges due to the need for advanced packaging and assembling techniques that enhance electrical performance and reduce transmission and insertion losses.
Innovation solutions
A semiconductor device manufacturing method involving a circuit substrate with build-up layers, semiconductor packages connected via interposers and underfills, and a metallic cover with grooves to enhance thermal dissipation and mechanical stability, allowing for efficient integration and packaging of multiple semiconductor devices.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If multiple semiconductor devices are integrated in miniaturized electronic apparatus, then device functionality and performance are improved, but transmission loss and insertion loss increase
Why choose this principle:
An interposer is introduced as an intermediary component between the circuit substrate and semiconductor packages. The interposer includes a first surface connected to the circuit substrate, a second surface connected to the semiconductor packages, and a side surface. This intermediary structure enables better signal transmission and reduces insertion loss by providing optimized signal paths and impedance matching between different components.
Principle concept:
If multiple semiconductor devices are integrated in miniaturized electronic apparatus, then device functionality and performance are improved, but transmission loss and insertion loss increase
Why choose this principle:
The patent transitions from traditional planar packaging to three-dimensional integration by stacking semiconductor packages vertically on the circuit substrate through the interposer. This vertical stacking approach increases device integration density while maintaining signal integrity by using through-silicon vias (TSVs) and controlled impedance structures in the vertical dimension.
Application Domain
Data Source
AI summary:
A semiconductor device manufacturing method involving a circuit substrate with build-up layers, semiconductor packages connected via interposers and underfills, and a metallic cover with grooves to enhance thermal dissipation and mechanical stability, allowing for efficient integration and packaging of multiple semiconductor devices.
Abstract
A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.