Noise Reduction in Solid-State Imaging Devices with Patent-Based Solutions
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Summary
Problems
Existing solid-state imaging devices face challenges in suppressing noise due to increased parasitic capacitance, reduced aperture ratio, and interference between readout wire lines, particularly in miniaturized designs.
Innovation solutions
The proposed imaging device includes a first chip with adjacent pixels and a second chip for signal processing, featuring specific wiring layers and vias configurations that minimize parasitic capacitance and noise by using insulating materials and strategic placement of anode and cathode electrodes and vias, along with shield wiring to reduce interference.
TRIZ Analysis
Specific contradictions:
General conflict description:
Principle concept:
If the quench circuit is arranged on the front surface side of the semiconductor substrate, then the light incident surface can be optimized, but the aperture ratio is decreased due to the space occupied by the quench circuit
Why choose this principle:
The patent moves the quench circuit from the front surface (2D plane) to the back surface of the semiconductor substrate, utilizing the third dimension (depth/thickness) to resolve the space conflict. This allows the front surface to be fully dedicated to light incident areas, maximizing aperture ratio while the quench circuit operates from the back surface without blocking light paths.
Principle concept:
If the quench circuit is arranged outside the active region of each pixel, then the pixel design flexibility is improved, but the aperture ratio is decreased
Why choose this principle:
The patent utilizes the back surface of the semiconductor substrate as an additional dimension for circuit placement. By arranging the quench circuit outside the active region on the back surface rather than on the front surface, the patent maintains pixel design flexibility while preventing the quench circuit from encroaching on the light-sensitive area, thus preserving aperture ratio.
Application Domain
Data Source
AI summary:
The proposed imaging device includes a first chip with adjacent pixels and a second chip for signal processing, featuring specific wiring layers and vias configurations that minimize parasitic capacitance and noise by using insulating materials and strategic placement of anode and cathode electrodes and vias, along with shield wiring to reduce interference.
Abstract
An imaging device includes a first chip. The first chip includes a first pixel and a second pixel. The first pixel includes a first anode region and a first cathode region, and the second pixel includes a second anode region and a second cathode region. The first chip includes a first wiring layer. The first wiring layer includes a first anode electrode, a first anode via coupled to the first anode electrode and the first anode region, and a second anode via coupled to the first anode electrode and the second anode region.