Semiconductor memory device

By using a three-dimensional semiconductor memory device with a vertically arranged common source electrode and gate electrode structure, the problem of decreased electrical characteristics caused by the reduction of memory cell size is solved, achieving high integration density and efficient operation.

CN111326518BActive Publication Date: 2025-12-23SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
CN201910858574.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2018-12-14
Filing Date
2019-09-11
Publication Date
2025-12-23
Estimated Expiration
2039-09-11

AI Technical Summary

Technical Problem

As memory cell size decreases and memory device integration density increases, electrical characteristics deteriorate, and existing technologies struggle to effectively address the complexity of operating circuits and wiring structures.

Method used

A semiconductor memory device with a three-dimensional structure includes a common source electrode, a substrate, multiple gate electrodes, an insulating film, and a channel structure. By forming a channel structure that penetrates the gate electrodes and the insulating film, combined with a remaining sacrificial film and a cell structure, a vertical layout is achieved to improve integration density.

Benefits of technology

The vertically arranged three-dimensional structure increases the integration density of the memory device, reduces the horizontal area, enhances electrical characteristics, and increases the number of memory cells and operating efficiency.

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Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a common source line, a substrate on the common source line, a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line, a plurality of insulating films arranged between the plurality of gate electrodes, a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulating films in the first direction, and a plurality of remaining sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of remaining sacrificial films.
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