Speed ​​controller analog signal input acquisition circuit and functional safety assurance method thereof

Abstract

The present invention relates to a speed control controller analog signal input acquisition circuit and a functional safety guarantee method thereof, which includes an analog signal input protection circuit, a dual-channel redundant signal sampling and acquisition circuit, a digital isolation circuit, and a functional safety CPU circuit, wherein the dual-channel redundant signal sampling and acquisition circuit includes a signal sampling and acquisition circuit A and a signal sampling and acquisition circuit B; the functional safety CPU circuit has built-in functional safety software, which calculates and distinguishes the received analog signal input acquisition results, realizes real-time monitoring of analog input faults, and triggers alarms or safety failure protection according to the severity of the fault, thereby ensuring the functional safety of a digital electronic speed control controller. The dual-channel redundant signal sampling and acquisition circuit designed by the present invention is relatively independent, and not only realizes abnormal monitoring of the sampling function of its data acquisition chip by sampling its own reference voltage, but also realizes mutual supervision by collecting the working status of the power supply voltage and reference voltage of the other party's data acquisition chip.

Description

Technical Field

[0001] The present invention relates to the technical field of digital electronic speed control controllers, and in particular to a speed control controller analog signal input acquisition circuit and a functional safety assurance method thereof. Background Art

[0002] Functional safety is a key technology to ensure the safe operation of equipment and systems in safety-critical fields such as nuclear power and petrochemicals. It aims to prevent dangerous accidents caused by design defects or random failures of safety-related devices. As a speed control device for diesel generator sets, turbine sets and many other equipment in the nuclear power and petrochemical industries, the functional safety of digital electronic speed controllers is of great value in ensuring the safe and reliable operation of related equipment and systems.

[0003] As the functional safety requirements of related industries continue to increase, traditional speed controllers have become increasingly difficult to meet actual application needs due to the lack of functional safety design. Analog signal acquisition is one of the basic functions required for digital electronic speed controllers. Traditional analog signal acquisition only completes basic data acquisition functions, lacks circuit safety and fault diagnosis capabilities, and is difficult to identify analog signal acquisition circuits themselves and abnormal signal failures, posing hidden dangers to the safe operation of equipment. For this reason, multiple analog signal acquisition modules can only be used to build redundant analog signal acquisition subsystems, or multiple speed controllers can be directly redundant to improve the safety and reliability of the system, resulting in complex system structure and high costs. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned shortcomings and provide an analog signal input acquisition circuit for a speed controller and a functional safety assurance method thereof. By combining the safety and diagnosability design of the analog signal input acquisition circuit with the functional safety software built into the functional safety CPU, the analog signal acquisition results are calculated and judged to achieve real-time monitoring of analog input and signal sampling and acquisition circuit faults, and trigger safety alarms or safety failure protection according to the severity of the fault, thereby ensuring the functional safety of the digital electronic speed controller.

[0005] The object of the present invention is achieved in that:

[0006] A speed controller analog signal input acquisition circuit comprises an analog signal input protection circuit, a dual-channel redundant signal sampling and acquisition circuit, a digital isolation circuit, and a functional safety CPU circuit. The dual-channel redundant signal sampling and acquisition circuit comprises a signal sampling and acquisition circuit A and a signal sampling and acquisition circuit B. The functional safety CPU circuit has built-in functional safety software, which calculates and distinguishes the received analog signal input acquisition results, realizes real-time monitoring of analog input faults, and triggers alarms or safety failure protection according to the severity of the fault, thereby ensuring the functional safety of the digital electronic speed controller.

[0007] Furthermore, the analog signal input protection circuit includes an input mode configuration resistor R7, capacitors C1A, C1B, C2A, C2B and C2C for ESD and EMI protection, magnetic beads FB1A, FB1B and TVS diodes TVSA, TVSB, TVSC, and self-recovery fuses FUSEA and FUSEB for input current limiting. The resistance of the configuration resistor R7 is 0. The input signal is connected to the common ground during welding, and the input signal is connected to the floating ground when not welding. The input signal SIG+ end is connected in parallel with the capacitor C1A, and then connected in parallel with the capacitor C2A and the TVS diode TVSA to the ground through the magnetic beads FB1A, self-recovery fuse FUSEA connected in series, to form a protected output signal AI+. The input signal SIG- end is connected in parallel with the capacitor C1B, and then connected in parallel with the capacitor C2B and the TVS diode TVSB to the ground through the magnetic beads FB1B, self-recovery fuse FUSEB connected in series, to form a protected output signal AI-. The capacitor C2C and the TVS diode TVSC are connected in parallel to the AI+ and AI- ends.

[0008] Furthermore, the signal sampling and acquisition circuit A includes an independent analog power supply A, a signal sampling and conditioning circuit A and an analog-to-digital conversion circuit A, and the signal sampling and acquisition circuit B includes an independent analog power supply B, a signal sampling and conditioning circuit B and an analog-to-digital conversion circuit B; the input signal is simultaneously connected to the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B, the signal sampling and conditioning circuit A is connected to the analog-to-digital conversion circuit A, and the signal sampling and conditioning circuit B is connected to the analog-to-digital conversion circuit B. In order to realize mutual supervision between the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B, the working power supply and reference voltage sampling signal V 5_A and REF_A are connected to the analog-to-digital conversion circuit B, the working power supply and reference voltage sampling signal V5_B and REF_B of the analog-to-digital conversion circuit B are connected to the analog-to-digital conversion circuit A, the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B simultaneously collect their own reference voltages REF_A and REF_B, the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B are respectively connected to the functional safety CPU circuit through the SPI-A and SPI-B interfaces, the analog power supply A provides power to the signal sampling and conditioning circuit A and the analog-to-digital conversion circuit A, and the analog power supply B provides power to the signal sampling and conditioning circuit B and the analog-to-digital conversion circuit B.

[0009] Furthermore, the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B are connected to the analog input signals AI+ and AI- through a common resistor R4 to realize the conversion of the analog current signal to the analog voltage signal. When the transmitter output signal is an analog voltage signal, the common resistor R4 is not welded, and the analog signal through the resistor R4 is respectively connected to the double voltage divider circuit composed of the resistor R1 and the resistors R9, R8 and the resistor R5 and the resistors R11, R12 to sample the analog signal. One sampling signal is connected to the instrument amplifier U1 through the resistors R2 and R6 to form the output signal SIG_A, and the other sampling signal is connected to the instrument amplifier U2 through the sampling voltage divider resistors R9 and R11 to form the output signal Signal SIG_B, the positive and negative input terminals of the instrument amplifiers U1 and U2 are connected in parallel with capacitors C4 and C7 respectively and are connected to the ground through capacitors C3 and C5 and capacitors C6 and C8 respectively to filter out common-mode and differential-mode interference. The instrument amplifiers U1 and U2 are connected with gain setting resistors R3 and R10 respectively to set the signal amplification factor. The reference voltages REF_A and REF_B of the instrument amplifiers U1 and U2 are respectively from the subsequent corresponding analog-to-digital conversion circuits A and analog-to-digital conversion circuits B. The access of the reference voltages REF_A and REF_B is used to identify the reverse connection of the analog input signal. If the output voltage of the instrument amplifiers U1 and U2 is less than the reference voltage value, the analog input signal is in a reverse connection state.

[0010] Furthermore, the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B have the same circuit structure, both of which include their own multi-channel analog-to-digital conversion chips and their reference voltage sampling circuits. The analog signals SIG_A0 to SIG_A3 come from the signal sampling and conditioning circuit A. SIG_A0 is connected to the multi-channel analog-to-digital conversion chip U3 through a symmetrical input circuit composed of resistors R13, R14 and capacitor C9. SIG_A1 to SIG_A3, the power supply sampling signal VAI_A of the signal sampling and conditioning circuit A, the reference voltage sampling signal REF_A of U3 itself, and the analog-to-digital conversion The analog power sampling signal V5_B and the reference voltage sampling signal REF_B of the multi-channel analog-to-digital conversion chip used in the conversion circuit B are connected to the multi-channel analog-to-digital conversion chip U3 through the same input circuit as SIG_A0. The reference voltage output signal REFOUT of the multi-channel analog-to-digital conversion chip U3 is grounded, filtered and decoupled by capacitor C18 and then connected to the first-stage voltage follower circuit composed of U4A through resistor R23. The output of U4A is divided by R26 and R28 and filtered by capacitor C20 and then connected to the second-stage voltage follower circuit composed of U4B to generate the reference voltage sampling signal REF_A.

[0011] Furthermore, the analog power supply A and the analog power supply B use a DC-DC isolation power supply module plus an LDO voltage regulator chip to generate the analog signal conditioning circuit power supplies VAI-A and VAI-B and the analog-to-digital conversion chip working power supplies VCC_A and VCC_B required by the dual-channel redundant signal sampling and acquisition circuit. The output power generated by the analog power supply A and the analog power supply B are grounded to facilitate the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B to monitor each other's working status.

[0012] Furthermore, the digital isolation circuit includes digital isolation chips U5, U7 and inverter circuits U6, U8. The digital isolation chip U5 and the inverter circuit U6 are used for electrical isolation of the analog-to-digital conversion circuit A and the SPIA interface of the functional safety CPU circuit. The digital isolation chip U7 and the inverter circuit U8 are used for electrical isolation of the analog-to-digital conversion circuit B and the SPIB interface of the functional safety CPU circuit. The three input signals INA, INB, and INC of the digital isolation chip U5 are respectively connected to the SPIA_CS#, SPIA_SCK, and SPIA_SCK of the SPIA port of the functional safety CPU circuit through the termination resistor RP1. _SI signal, the digital isolation chip U5 output signal OUTD is connected to the SPIA_SO signal of the functional safety CPU circuit SPIA port through the termination resistor RP1, the SPIA_CS# signal is connected to the EN1 pin of U5 through the inverter U6 to ensure that the OUTD output of U5 is in a high-impedance state when the SPIA_CS# signal is high, the three output signals OUTA, OUTB, OUTC and the input signal IND of U5 are connected to the multi-channel analog-to-digital conversion chip U3, and the circuit formed by the digital isolation chip U7 and the inverter U8 has the same circuit structure as the circuit formed by the digital isolation chip U5 and the inverter U6.

[0013] Furthermore, the functional safety CPU circuit includes a functional safety CPU, a functional failure relay output circuit and an alarm relay output circuit. The functional safety CPU has two serial peripheral interfaces SPIA and SPIB, which are respectively connected to the analog-digital conversion circuit A and the analog-digital conversion circuit B for controlling the operation of the analog-digital conversion circuit A and the analog-digital conversion circuit B and reading the data collected by the analog-digital conversion circuit A and the analog-digital conversion circuit B. The two serial peripheral interfaces SPIA and SPIB can also use only one SPI interface of the functional safety CPU to control the SPIA_CS# and SPIB_CS# signals through its additional I / O pins in a time-sharing manner. The functional failure relay output circuit includes resistors R42, R43, R44, transistor Q1, diode D1 and relay RELAY. The hardware embedded in the functional safety CPU The self-diagnosis status output pin nERROR and its software-controlled general I / O interface signal GPIOn are connected to the base of the transistor Q1 through resistors R43 and R42 respectively. The base of the transistor is pulled up to the +3.3V power supply through resistor R44 at the same time. Resistors R42, R43, R44 and transistor Q1 form a logic "AND" circuit. As long as one of the nERROR and GPIOn signals outputs a low level, the transistor can be triggered to turn on to make the functional safety status relay RELAY actuated. The diode D1 is connected in reverse parallel to both ends of the relay RELAY drive coil pin for coil continuous current. The relay output normally open contact ERR_NO, normally closed contact ERR_NC and common contact ERR_COM are output and connected to the external safety system to ensure system-level functional safety. The alarm relay output circuit is used to output a non-functional failure alarm signal of the speed controller.

[0014] Furthermore, the functional safety software embedded in the functional safety CPU circuit controls and obtains all analog signal values ​​collected by the dual-channel redundant signal sampling and acquisition circuit through the SPI peripheral expansion interface, determines the working state and analog input signal state of the dual-channel redundant signal sampling and acquisition circuit by comparison with the nominal signal value and logical judgment, and determines the final output analog signal value for subsequent control by the speed controller; when the dual-channel redundant signal sampling and acquisition circuit or the analog signal fails at the same time or the functional safety CPU itself fails seriously, a functional failure alarm output is issued according to the functional safety requirements for the upper-level system to complete the functional safety operation.

[0015] A functional safety assurance method for a speed controller analog signal input acquisition circuit comprises the following steps:

[0016] Step 1: The system is powered on and started to run. According to the data acquisition cycle, the analog signal acquisition process is entered. First, the functional safety software embedded in the functional safety CPU circuit controls the dual-channel redundant signal sampling and acquisition circuits through the SPI interface to perform data acquisition.

[0017] Step 2: After the dual-channel redundant signal sampling and acquisition circuit completes data acquisition of all input channels, the functional safety software embedded in the functional safety CPU circuit reads the data acquisition results of the dual-channel redundant analog-to-digital conversion chip through the SPI interface;

[0018] Step 3: collect data of the analog signal obtained in step 2, and determine whether its sampling function is normal through the acquisition result of the reference voltage sampling signal of the analog-to-digital conversion circuit, and set the corresponding sampling function normal or not flag bSampOK_A or bSampOK_B. The judgment logic is as follows:

[0019]

[0020] In the formula, n is A or B, V REF is the nominal reference voltage value of the analog-to-digital conversion circuit, V SelfREF_n is the reference voltage value collected by the analog-to-digital conversion circuit, δ REF is the reference voltage allowable error;

[0021] Step 4: collect data of the analog signal obtained in step 2, determine whether the working power supply of analog-to-digital conversion circuit B is normal through the collection results of the analog power supply and reference voltage of analog-to-digital conversion circuit B collected by analog-to-digital conversion circuit A, and set the normal or not flag bADPwrOK_B; determine whether the working power supply of analog-to-digital conversion circuit A is normal through the collection results of the analog power supply and reference voltage of analog-to-digital conversion circuit A collected by analog-to-digital conversion circuit B, and set the normal or not flag bADPwrOK_A;

[0022] Step 5: judging and setting the normality flags bADOK_A and bADOK_B of the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B according to the bSampOK_A, bSampOK_B, bADPwrOK_A, and bADPwrOK_B status flags determined in step 3 and step 4;

[0023] Step 6: for the analog signal acquisition data obtained in step 2, according to the acquisition results of the power supply sampling signals of the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B, determine whether the power supply of the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B is normal or not, bAIPwrOK_A and bAIPwrOK_B;

[0024] Step 7: For the flags bADOK_A, bADOK_B and bAIPwrOK_A, bAIPwrOK_B determined in step 5 and step 6, determine whether the hardware working status of the signal sampling and acquisition circuit A and the signal sampling and acquisition circuit B is normal or not, flags bHardwareOK_A and bHardwareOK_B according to the following judgment logic:

[0025]

[0026] Step 8: for the external transmitter analog signal acquisition data obtained in step 2 and the flags bHardwareOK_A and bHardwareOK_B determined in step 7, determine the states bSigOK_Am and bSigOK_Bm of the m-th analog input signal acquired by the signal sampling and acquisition circuit A and the signal sampling and acquisition circuit B according to the following judgment logic:

[0027]

[0028] Where n is A or B, m=0, 1, 2, ... represents the m+1th analog input signal, V SIG_nm is the voltage value of the mth analog input signal collected by the first signal sampling and acquisition circuit 2A or the second signal sampling and acquisition circuit 2B, V SIG_mLowest and V SIG_mHighest They are the lower limit and upper limit of the m+1th analog input signal value respectively;

[0029] Step 9: According to the final analog signal sampling value of the analog input signal status flags bSigOK_Am and bSigOK_Bm determined in step 8, if bSigOK_Am=TRUE, bSigOK_Bm=TRUE, then the analog signal sampling output: Determine the final signal sampling value according to the analog input selection logic configured by the functional safety software; if bSigOK_Am=TRUE, bSigOK_Bm=FALSE, then the analog signal sampling output is V SIG_Am ; If bSigOK_Am=FALSE、bSigOK_Bm=TRUE, the analog signal sampling output is V SIG_Bm ; If bSigOK_Am=FALSE, bSigOK_Bm=FALSE, the analog signal sampling output: if the speed controller is in standby state, an alarm will be issued and the speed controller will be prohibited from starting; if the speed controller is in running state, an alarm will be issued and the sampling value in the previous normal state will be taken as the final sampling value or the controller will be shut down directly according to the configuration of the functional safety software.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] (1) The hardware circuit of the present invention adopts a safety and diagnosability design, combined with the functional safety software built into the functional safety CPU, which not only realizes the abnormal monitoring of the analog input signal, but also realizes the real-time monitoring of the fault of the signal sampling and acquisition circuit itself, and can trigger a safety alarm or safety failure protection according to the severity of the fault, effectively ensuring the functional safety of the digital electronic speed controller;

[0032] (2) The dual-path redundant signal sampling and acquisition circuit designed in the present invention is relatively independent. It not only realizes abnormal monitoring of the sampling function of its data acquisition chip by sampling its own reference voltage, but also realizes mutual supervision by sampling the working status of the power supply voltage and reference voltage of the other party's data acquisition chip, thus avoiding the deficiency of the traditional redundant circuit being completely independent and only being able to perform redundant judgment on its output signal, thereby further improving its reliability.

[0033] (3) The present invention integrates multiple hardware safety protections, not only realizing ESD and EMI protection by combining magnetic beads, capacitors and TVS diodes, but also limiting the current by self-recovery fuses, effectively ensuring the safety of the TVS diode itself in the event of continuous overvoltage or overcurrent, and improving the fault protection capability of the circuit;

[0034] (4) The present invention implements accident warning to users through non-functional failure fault alarms, and transmits information to the upper-level functional safety system through functional failure output in emergency situations to achieve system-level emergency functional safety protection, further improving the safety protection level of equipment speed control. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the overall circuit principle of the present invention.

[0036] Figure 2 It is a schematic diagram of the principle of the analog input protection circuit of the present invention.

[0037] Figure 3 It is a schematic diagram of the principle of the dual-path redundant signal sampling and acquisition circuit of the present invention.

[0038] Figure 4 It is a schematic diagram of the signal sampling and conditioning circuit principle of the present invention.

[0039] Figure 5 It is a schematic diagram of the principle of the analog-to-digital conversion circuit of the present invention.

[0040] Figure 6 It is a schematic diagram of the principle of the analog power supply circuit of the present invention.

[0041] Figure 7 It is a schematic diagram of the principle of the digital isolation circuit of the present invention.

[0042] Figure 8It is a schematic diagram of the functional safety CPU circuit principle of the present invention.

[0043] Fig. 9 This is a flowchart of the functional safety assurance software of the present invention.

[0044] in:

[0045] Analog signal input protection circuit 1, first signal sampling and acquisition circuit 2A, first analog power supply 20A, first signal sampling and conditioning circuit 21A, first analog-to-digital conversion circuit 22A, second signal sampling and acquisition circuit 2B, second analog power supply 20B, second signal sampling and conditioning circuit 21B, second analog-to-digital conversion circuit 22B, digital isolation circuit 3, functional safety CPU circuit 4, functional safety CPU 40, functional failure relay output circuit 41, alarm relay output circuit 42. DETAILED DESCRIPTION

[0046] See also Figure 1-9 The present invention relates to an analog signal input acquisition circuit of a speed controller, which includes an analog signal input protection circuit 1, a dual-channel redundant signal sampling and acquisition circuit, a digital isolation circuit 3, and a functional safety CPU circuit 4. The dual-channel redundant signal sampling and acquisition circuit includes a first signal sampling and acquisition circuit 2A and a second signal sampling and acquisition circuit 2B; the functional safety CPU circuit 4 has built-in functional safety software, which calculates and distinguishes the received analog signal input acquisition results, realizes real-time monitoring of analog input faults, and triggers alarms or safety failure protection according to the severity of the fault, thereby ensuring the functional safety of the digital electronic speed controller.

[0047] like Figure 2 As shown, the analog signal input protection circuit 1 includes an input mode configuration resistor R7, capacitors C1A, C1B, C2A, C2B and C2C for ESD and EMI protection, magnetic beads FB1A, FB1B and TVS diodes TVSA, TVSB, TVSC, and self-recovery fuses FUSEA and FUSEB for input current limiting. The resistance of the configuration resistor R7 is 0. The input signal is connected to the common ground during welding, and the input signal is connected to the floating ground when not welding. The input signal SIG+ terminal is connected in parallel with the capacitor C1A and then connected in parallel with the capacitor C2A and the TVS diode TVSA to the ground via the magnetic beads FB1A, self-recovery fuse FUSEA connected in series, and then connected in parallel with the capacitor C2A and the TVS diode TVSA to form a protected output signal AI+. The input signal SIG- terminal is connected in parallel with the capacitor C1B and then connected in parallel with the magnetic beads FB1B, self-recovery fuse FUSEB, capacitor C2B and the TVS diode TVSB to the ground via the magnetic beads FB1B, self-recovery fuse FUSEB, capacitor C2B and the TVS diode TVSB to the ground to form a protected output signal AI-. The capacitor C2C and the TVS diode TVSC are connected in parallel to the AI+ and AI- terminals.

[0048] like Figure 3 As shown, the first signal sampling and acquisition circuit 2A includes an independent first analog power supply 20A, a first signal sampling and conditioning circuit 21A and a first analog-to-digital conversion circuit 22A, and the second signal sampling and acquisition circuit 2B includes an independent second analog power supply 20B, a second signal sampling and conditioning circuit 21B and a second analog-to-digital conversion circuit 22B; the input signal is simultaneously connected to the first signal sampling and conditioning circuit 21A and the second signal sampling and conditioning circuit 21B, the first signal sampling and conditioning circuit 21A is connected to the first analog-to-digital conversion circuit 22A, and the second signal sampling and conditioning circuit 21B is connected to the second analog-to-digital conversion circuit 22B. In order to realize mutual supervision between the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B, the working power supply and reference of the first analog-to-digital conversion circuit 22A are connected to the first analog-to-digital conversion circuit 22A. The voltage sampling signals V5_A and REF_A are connected to the second analog-to-digital conversion circuit 22B, the working power supply and reference voltage sampling signals V5_B and REF_B of the second analog-to-digital conversion circuit 22B are connected to the first analog-to-digital conversion circuit 22A, the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B simultaneously collect their own reference voltages REF_A and REF_B, the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B are respectively connected to the functional safety CPU circuit 4 through the SPI-A and SPI-B interfaces, the first analog power supply 20A provides power to the first signal sampling and conditioning circuit 21A and the first analog-to-digital conversion circuit 22A, and the second analog power supply 20B provides power to the second signal sampling and conditioning circuit 21B and the second analog-to-digital conversion circuit 22B.

[0049] like Figure 4As shown, the first signal sampling and conditioning circuit 21A and the second signal sampling and conditioning circuit 21B are connected to the analog input signals AI+ and AI- through a common resistor R4 to realize the conversion of the analog current signal to the analog voltage signal. When the transmitter output signal is an analog voltage signal, the common resistor R4 is not welded, and the analog signal through the resistor R4 is respectively connected to the double voltage divider circuit composed of the resistor R1 and the resistors R9 and R8 and the resistor R5 and the resistors R11 and R12 to sample the analog signal. One sampling signal is connected to the instrument amplifier U1 through the resistors R2 and R6 to form the output signal SIG_A, and the other sampling signal is connected to the instrument amplifier U2 through the sampling voltage divider resistors R9 and R11 To form an output signal SIG_B, the positive and negative input terminals of the instrument amplifiers U1 and U2 are connected in parallel with capacitors C4 and C7 respectively and are connected to the ground through capacitors C3 and C5 and capacitors C6 and C8 respectively to filter out common-mode and differential-mode interference. The instrument amplifiers U1 and U2 are connected with gain setting resistors R3 and R10 respectively to set the signal amplification factor. The reference voltages REF_A and REF_B of the instrument amplifiers U1 and U2 are respectively derived from the subsequent corresponding analog-to-digital conversion circuits 22A and 22B. The access to the reference voltages REF_A and REF_B is used to identify the reverse connection of the analog input signal. If the output voltage of the instrument amplifiers U1 and U2 is less than the reference voltage value, the analog input signal is in a reverse connection state.

[0050] like Figure 5 As shown, the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B have the same circuit structure, both of which include their own multi-channel analog-to-digital conversion chips and their reference voltage sampling circuits. Taking the first analog-to-digital conversion circuit 22A as an example, the analog signals SIG_A0 to SIG_A3 come from the first signal sampling and conditioning circuit 21A, SIG_A0 is connected to the multi-channel analog-to-digital conversion chip U3 through a symmetrical input circuit composed of resistors R13, R14 and capacitor C9, SIG_A1 to SIG_A3, the power supply sampling signal VAI_A of the first signal sampling and conditioning circuit 21A, and the reference voltage sampling circuit of U3 itself. The sampling signal REF_A and the analog power sampling signal V5_B and the reference voltage sampling signal REF_B of the multi-channel analog-to-digital conversion chip used in the second analog-to-digital conversion circuit 22B are all connected to the multi-channel analog-to-digital conversion chip U3 through the same input circuit as SIG_A0. The reference voltage output signal REFOUT of the multi-channel analog-to-digital conversion chip U3 is grounded, filtered and decoupled by capacitor C18 and then connected to the first-stage voltage follower circuit formed by U4A through resistor R23. The output of U4A is divided by R26 and R28 and filtered by capacitor C20 and then connected to the second-stage voltage follower circuit formed by U4B to generate the reference voltage sampling signal REF_A.

[0051] like Figure 6As shown, the first analog power supply 20A and the second analog power supply 20B use a DC-DC isolation power supply module plus an LDO voltage regulator chip to generate the analog signal conditioning circuit power supplies VAI-A, VAI-B and the analog-to-digital conversion chip working power supplies VCC_A, VCC_B required by the dual redundant signal sampling and acquisition circuits 2A and 2B. The output power supplies generated by the analog power supplies 20A and 20B share a common ground to facilitate the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B to monitor each other's working status.

[0052] like Figure 7 As shown, the digital isolation circuit includes digital isolation chips U5, U7 and inverter circuits U6, U8. The digital isolation chip U5 and the inverter circuit U6 are used for electrical isolation of the first analog-to-digital conversion circuit 22A and the SPIA interface of the functional safety CPU circuit 4. The digital isolation chip U7 and the inverter circuit U8 are used for electrical isolation of the second analog-to-digital conversion circuit 22B and the 4SPIB interface of the functional safety CPU circuit 4. The three input signals INA, INB, and INC of the digital isolation chip U5 are respectively connected to the functional The SPIA_CS#, SPIA_SCK, and SPIA_SI signals of the SPIA port of the safety CPU circuit 4, the output signal OUTD of the digital isolation chip U5 is connected to the SPIA_SO signal of the SPIA port of the functional safety CPU circuit 4 through the termination resistor RP1, and the SPIA_CS# signal is connected to the EN1 pin of U5 through the inverter U6 to ensure that the OUTD output of U5 is in a high-impedance state when the SPIA_CS# signal is high, and the three output signals OUTA, OUTB, OUTC of U5 and the input signal IND are connected to Figure 5 The circuit structure formed by the multi-channel analog-to-digital conversion chip U3, the digital isolation chip U7 and the inverter U8 is the same as the circuit structure formed by the digital isolation chip U5 and the inverter U6.

[0053] like Figure 8As shown, the functional safety CPU circuit 4 includes a functional safety CPU 40, a functional failure relay output circuit 41 and an alarm relay output circuit 42. The functional safety CPU 40 has two serial peripheral interfaces SPIA and SPIB respectively connected to the analog-to-digital conversion circuits 22A and 22B for controlling the operation of the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B and reading the data collected by the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B. The two serial peripheral interfaces SPIA and SPIB can also be used only with the functional safety CPU The SPI interface of 40 is realized by time-sharing control of SPIA_CS# and SPIB_CS# signals through its additional I / O pins. The functional failure relay output circuit 41 includes resistors R42, R43, R44, transistor Q1, diode D1 and relay RELAY. The hardware self-diagnosis status output pin nERROR embedded in the functional safety CPU 40 and its software-controlled general I / O interface signal GPIOn are connected to the base of the transistor Q1 through resistors R43 and R42 respectively. The base of the transistor is pulled up to the +3.3V power supply through resistor R44. Resistors R42, R43, R44 and the transistor Q1 are connected to the base of the transistor Q1 through resistor R43 and R42 respectively. The transistor Q1 forms a logic "AND" circuit. As long as one of the nERROR and GPIOn signals outputs a low level, the transistor can be triggered to conduct, allowing the functional safety status relay RELAY to operate. The diode D1 is connected in reverse parallel to both ends of the relay RELAY drive coil pin for coil continuous current. The relay output normally open contact ERR_NO, normally closed contact ERR_NC and common contact ERR_COM are output and connected to the external safety system to ensure system-level functional safety. The principle of the alarm relay output circuit 42 is similar to that of the functional failure relay output circuit 41, and is used to output a non-functional failure fault alarm signal of the speed controller.

[0054] like Fig. 9 As shown, the functional safety software embedded in the functional safety CPU circuit 4 controls and obtains all analog signal values ​​collected by the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B through the SPI peripheral expansion interface, determines the working state and analog input signal state of the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B by comparison with the nominal signal value and logical judgment, and determines the final output analog signal value for subsequent control by the speed controller. When the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B or the analog signal fails at the same time or the functional safety CPU 40 itself fails seriously, a functional failure alarm output is issued according to the functional safety requirements for the upper-level system to complete the functional safety operation.

[0055] The present invention relates to a method for ensuring an analog signal input acquisition circuit of a speed control controller, which comprises the following steps:

[0056] (1) The system is powered on and started to run, and enters the analog signal acquisition process according to the data acquisition cycle. First, the functional safety software embedded in the functional safety CPU circuit 4 controls the dual-channel redundant signal sampling and acquisition circuits through the SPI interface to perform data acquisition;

[0057] (2) After the data acquisition of all input channels of the dual-channel redundant signal sampling and acquisition circuit is completed, the functional safety software embedded in the functional safety CPU circuit 4 reads the data acquisition results of the dual-channel redundant analog-to-digital conversion chip through the SPI interface.

[0058] (3) For the analog signal acquisition data obtained in step (2), the acquisition result of the reference voltage sampling signal of the analog-to-digital conversion circuit is used to determine whether its sampling function is normal, and the corresponding sampling function normal or not flag bSampOK_A or bSampOK_B is set. The determination logic is as follows:

[0059]

[0060] In the formula, n is A or B, V REF is the nominal reference voltage value of the analog-to-digital conversion circuit, V SelfREF_n is the reference voltage value collected by the analog-to-digital conversion circuit, δ REF is the allowable error of the reference voltage.

[0061] (4) For the analog signal acquisition data obtained in step (2), whether the working power supply of the second analog-to-digital conversion circuit 22B is normal is determined by the acquisition results of the analog power supply and reference voltage of the second analog-to-digital conversion circuit 22B acquired by the first analog-to-digital conversion circuit 22A, and a normal or not flag bADPwrOK_B is set; whether the working power supply of the first analog-to-digital conversion circuit 22A is normal is determined by the acquisition results of the analog power supply and reference voltage of the first analog-to-digital conversion circuit 22A acquired by the second analog-to-digital conversion circuit 22B, and a normal or not flag bADPwrOK_A is set. The judgment logic is as follows:

[0062]

[0063]

[0064] In the above two equations, V 5V and V REF are the nominal analog power supply and reference voltage value of the analog-to-digital conversion circuit, V V5_A and V REF_Aare respectively the analog power supply and reference voltage value of the first analog-to-digital conversion circuit 22A collected by the second analog-to-digital conversion circuit 22B, V V5_B and V REF_B are respectively the analog power supply and reference voltage value of the second analog-to-digital conversion circuit 22B collected by the first analog-to-digital conversion circuit 22A, δ 5V and δ REF It is the allowable error of the analog power supply and reference voltage for the analog-to-digital conversion circuit.

[0065] (5) According to the bSampOK_A, bSampOK_B, bADPwrOK_A, bADPwrOK_B status flags determined in steps (3) and (4), the normality flags bADOK_A and bADOK_B of the first analog-to-digital conversion circuit 22A and the second analog-to-digital conversion circuit 22B are judged and set. The judgment logic is as follows:

[0066]

[0067] Where n is A or B.

[0068] (6) For the analog signal acquisition data acquired in step (2), according to the acquisition results of the power supply sampling signals of the first signal sampling and conditioning circuit 21A and the second signal sampling and conditioning circuit 21B, the power supply normality flags bAIPwrOK_A and bAIPwrOK_B of the first signal sampling and conditioning circuit 21A and the second signal sampling and conditioning circuit 21B are judged, and the judgment logic is as follows:

[0069]

[0070] In the formula, n is A or B, V VAI is the nominal power supply voltage of the signal sampling and conditioning circuit, V VAI_n is the signal sampling and conditioning circuit power supply voltage acquisition result, δ VAI It is the allowable error of the power supply voltage of the signal sampling and conditioning circuit.

[0071] (7) For the flags bADOK_A, bADOK_B and bAIPwrOK_A, bAIPwrOK_B determined in steps (5) and (6), the flags bHardwareOK_A and bHardwareOK_B of whether the hardware working status of the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B is normal or not are determined according to the following judgment logic:

[0072]

[0073] (8) For the external transmitter analog signal acquisition data acquired in step (2) and the flags bHardwareOK_A and bHardwareOK_B determined in step (7), the states bSigOK_Am and bSigOK_Bm of the m-th analog input signal acquired by the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B are determined according to the following judgment logic:

[0074]

[0075] Where n is A or B, m=0, 1, 2, ... represents the m+1th analog input signal, V SIG_nm is the voltage value of the mth analog input signal collected by the first signal sampling and acquisition circuit 2A or the second signal sampling and acquisition circuit 2B, V SIG_mLowest and V SIG_mHighest They are respectively the lower limit and upper limit of the m+1th analog input signal value.

[0076] (9) According to the analog input signal status flags bSigOK_Am and bSigOK_Bm determined in step (8), the final analog signal sampling value is determined according to the following logic truth table:

[0077]

[0078] The final sampled output value when the analog input selection logic is configured to take the main channel value, take the larger value, take the smaller value, or take the average value is as follows:

[0079]

[0080] Where m=0, 1, 2, ... represents the m+1th analog input signal, V SIG_mMain , V SIG_mMax , V SIG_mMin and V SIG_mMean The final m+1 analog signal sampling output value when the analog input selection logic is configured to take the main channel value, take the maximum value, take the minimum value, and take the average value, respectively. V SIG_Am and V SIG_Bm They are respectively the collection results of the first signal sampling and acquisition circuit 2A and the second signal sampling and acquisition circuit 2B on the m+1th analog input signal.

[0081] The above are only specific application examples of the present invention and do not constitute any limitation on the protection scope of the present invention. Any technical solution formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the present invention.

Claims

1. A speed controller analog signal input acquisition circuit, characterized in that: It includes an analog signal input protection circuit, a dual-channel redundant signal sampling and acquisition circuit, a digital isolation circuit, and a functional safety CPU circuit. The dual-channel redundant signal sampling and acquisition circuit includes a signal sampling and acquisition circuit A and a signal sampling and acquisition circuit B. The functional safety CPU circuit has built-in functional safety software to calculate and judge the received analog signal input acquisition results, realize real-time monitoring of analog input faults, and trigger alarms or safety failure protection according to the severity of the faults, thereby ensuring the functional safety of the digital electronic speed control controller. The analog signal input protection circuit includes an input mode configuration resistor R7, capacitors C1A, C1B, C2A, C2B and C2C for ESD and EMI protection, magnetic beads FB1A, FB1B and TVS diodes TVSA, TVSB, TVSC, and self-recovery fuses FUSEA and FUSEB for input current limiting. The resistance of the configuration resistor R7 is 0. The input signal is connected to the common ground when welding, and the input signal is connected to the floating ground when not welding. The input signal SIG+ terminal is connected in parallel with the capacitor C1A, and then connected in parallel with the capacitor C2A and the TVS diode TVSA to the ground via the magnetic beads FB1A, self-recovery fuse FUSEA connected in series, to form a protected output signal AI+. The input signal SIG- terminal is connected in parallel with the capacitor C1B, and then connected in parallel with the capacitor C2B and the TVS diode TVSB to the ground via the magnetic beads FB1B, self-recovery fuse FUSEB connected in series, to form a protected output signal AI-. The capacitor C2C and the TVS diode TVSC are connected in parallel to the AI+ and AI- terminals; The signal sampling and acquisition circuit A includes an independent analog power supply A, a signal sampling and conditioning circuit A and an analog-to-digital conversion circuit A, and the signal sampling and acquisition circuit B includes an independent analog power supply B, a signal sampling and conditioning circuit B and an analog-to-digital conversion circuit B; the input signal is simultaneously connected to the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B, the signal sampling and conditioning circuit A is connected to the analog-to-digital conversion circuit A, and the signal sampling and conditioning circuit B is connected to the analog-to-digital conversion circuit B. In order to realize mutual supervision between the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B, the working power supply and reference voltage sampling signal V5_A of the analog-to-digital conversion circuit A are and REF_A are connected to the analog-to-digital conversion circuit B, the working power supply and reference voltage sampling signal V5_B and REF_B of the analog-to-digital conversion circuit B are connected to the analog-to-digital conversion circuit A, the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B simultaneously collect their own reference voltages REF_A and REF_B, the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B are respectively connected to the functional safety CPU circuit through the SPI-A and SPI-B interfaces, the analog power supply A provides power to the signal sampling and conditioning circuit A and the analog-to-digital conversion circuit A, and the analog power supply B provides power to the signal sampling and conditioning circuit B and the analog-to-digital conversion circuit B; The digital isolation circuit includes digital isolation chips U5, U7 and inverter circuits U6, U8. The digital isolation chip U5 and the inverter circuit U6 are used for electrical isolation of the analog-to-digital conversion circuit A and the SPIA interface of the functional safety CPU circuit. The digital isolation chip U7 and the inverter circuit U8 are used for electrical isolation of the analog-to-digital conversion circuit B and the SPIB interface of the functional safety CPU circuit. The three input signals INA, INB, and INC of the digital isolation chip U5 are respectively connected to SPIA_CS#, SPIA_SCK, and SPIA_S of the SPIA port of the functional safety CPU circuit through the termination resistor RP1. I signal, the output signal OUTD of the digital isolation chip U5 is connected to the SPIA_SO signal of the functional safety CPU circuit SPIA port through the termination resistor RP1, the SPIA_CS# signal is connected to the EN1 pin of U5 through the inverter U6 to ensure that the OUTD output of U5 is in a high-impedance state when the SPIA_CS# signal is high, the three output signals OUTA, OUTB, OUTC and the input signal IND of U5 are connected to the multi-channel analog-to-digital conversion chip U3, and the circuit formed by the digital isolation chip U7 and the inverter U8 has the same circuit structure as the circuit formed by the digital isolation chip U5 and the inverter U6; The functional safety CPU circuit includes a functional safety CPU, a functional failure relay output circuit and an alarm relay output circuit. The functional safety CPU has two serial peripheral interfaces SPIA and SPIB, which are respectively connected to the analog-digital conversion circuit A and the analog-digital conversion circuit B to control the operation of the analog-digital conversion circuit A and the analog-digital conversion circuit B and read the data collected by the analog-digital conversion circuit A and the analog-digital conversion circuit B. The two serial peripheral interfaces SPIA and SPIB use the one SPI interface of the functional safety CPU to control the SPIA_CS# and SPIB_CS# signals through its additional I / O pins. The functional failure relay output circuit includes resistors R42, R43, R44, transistor Q1, diode D1 and relay RELAY. The hardware self-diagnosis status of the functional safety CPU is embedded in the functional safety CPU. The state output pin nERROR and its software-controlled general I / O interface signal GPIOn are connected to the base of the transistor Q1 through resistors R43 and R42 respectively. The base of the transistor is pulled up to the +3.3V power supply through resistor R44 at the same time. Resistors R42, R43, R44 and transistor Q1 form a logic "AND" circuit. As long as one of the nERROR and GPIOn signals outputs a low level, the transistor can be triggered to turn on to make the functional safety status relay RELAY actuated. The diode D1 is connected in reverse parallel to both ends of the relay RELAY drive coil pin for coil continuous current. The relay output normally open contact ERR_NO, normally closed contact ERR_NC and common contact ERR_COM are output and connected to the external safety system to ensure system-level functional safety. The alarm relay output circuit is used to output a non-functional failure alarm signal of the speed controller.

2. The analog signal input acquisition circuit of a speed controller according to claim 1, characterized in that: The signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B are connected to the analog input signals AI+ and AI- through a common resistor R4 to realize the conversion of analog current signals to analog voltage signals. When the output signal of the transmitter is an analog voltage signal, the common resistor R4 is not welded, and the analog signal through the resistor R4 is respectively connected to the double voltage divider circuit composed of resistor R1 and resistors R9, R8 and resistor R5 and resistors R11, R12 to sample the analog signal. One sampling signal is connected to the instrument amplifier U1 through resistors R2 and R6 to form the output signal SIG_A, and the other sampling signal is connected to the instrument amplifier U2 through the sampling voltage divider resistors R9 and R11 to form the output signal SI G_B, the positive and negative input terminals of the instrument amplifiers U1 and U2 are connected in parallel with capacitors C4 and C7 respectively and are connected to the ground through capacitors C3 and C5 and capacitors C6 and C8 respectively to filter out common-mode and differential-mode interference. The instrument amplifiers U1 and U2 are connected with gain setting resistors R3 and R10 respectively to set the signal amplification factor. The reference voltages REF_A and REF_B of the instrument amplifiers U1 and U2 come from the subsequent corresponding analog-to-digital conversion circuits A and analog-to-digital conversion circuits B respectively. The access of the reference voltages REF_A and REF_B is used to identify the reverse connection of the analog input signal. If the output voltage of the instrument amplifiers U1 and U2 is less than the reference voltage value, the analog input signal is in a reverse connection state.

3. The analog signal input acquisition circuit of a speed controller according to claim 1, characterized in that: The analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B have the same circuit structure, and both include their own multi-channel analog-to-digital conversion chips and their reference voltage sampling circuits. The analog signals SIG_A0 to SIG_A3 come from the signal sampling and conditioning circuit A. SIG_A0 is connected to the multi-channel analog-to-digital conversion chip U3 through a symmetrical input circuit composed of resistors R13, R14 and capacitor C9. SIG_A1 to SIG_A3, the power supply sampling signal VAI_A of the signal sampling and conditioning circuit A, the reference voltage sampling signal REF_A of U3 itself, and the analog-to-digital conversion circuit The analog power sampling signal V5_B and the reference voltage sampling signal REF_B of the multi-channel analog-to-digital conversion chip used by B are both connected to the multi-channel analog-to-digital conversion chip U3 through the same input circuit as SIG_A0. The reference voltage output signal REFOUT of the multi-channel analog-to-digital conversion chip U3 is grounded, filtered and decoupled by capacitor C18 and then connected to the first-stage voltage follower circuit formed by U4A through resistor R23. The output of U4A is divided by R26 and R28 and filtered by capacitor C20 and then connected to the second-stage voltage follower circuit formed by U4B to generate the reference voltage sampling signal REF_A.

4. The analog signal input acquisition circuit of a speed controller according to claim 1, characterized in that: The analog power supply A and the analog power supply B use a DC-DC isolation power supply module plus an LDO voltage regulator chip to generate the analog signal conditioning circuit power supplies VAI-A and VAI-B and the analog-to-digital conversion chip working power supplies VCC_A and VCC_B required by the dual-channel redundant signal sampling and acquisition circuit. The output power generated by the analog power supply A and the analog power supply B share a common ground to facilitate the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B to monitor each other's working status.

5. The analog signal input acquisition circuit of a speed controller according to claim 1, characterized in that: The functional safety software embedded in the functional safety CPU circuit controls and obtains all analog signal values ​​collected by the dual-channel redundant signal sampling and acquisition circuit through the SPI peripheral expansion interface, determines the working state and analog input signal state of the dual-channel redundant signal sampling and acquisition circuit by comparison with the nominal signal value and logical judgment, and determines the final output analog signal value for subsequent control of the speed controller; when the dual-channel redundant signal sampling and acquisition circuit or the analog signal fails at the same time or the functional safety CPU itself fails seriously, a functional failure alarm output is issued according to the functional safety requirements for the upper-level system to complete the functional safety operation.

6. A functional safety assurance method for the analog signal input acquisition circuit of a speed controller according to claim 1, characterized in that: It includes the following steps: Step 1: The system is powered on and started to run. According to the data acquisition cycle, the analog signal acquisition process is entered. First, the functional safety software embedded in the functional safety CPU circuit controls the dual-channel redundant signal sampling and acquisition circuits through the SPI interface to perform data acquisition. Step 2: After the dual-channel redundant signal sampling and acquisition circuit completes data acquisition of all input channels, the functional safety software embedded in the functional safety CPU circuit reads the data acquisition results of the dual-channel redundant analog-to-digital conversion chip through the SPI interface; Step 3: collect data of the analog signal obtained in step 2, and determine whether its sampling function is normal through the acquisition result of the reference voltage sampling signal of the analog-to-digital conversion circuit, and set the corresponding sampling function normal or not flag bSampOK_A or bSampOK_B. The judgment logic is as follows: In the formula, n is A or B, V REF is the nominal reference voltage value of the analog-to-digital conversion circuit, V SelfREF_n is the reference voltage value collected by the analog-to-digital conversion circuit, δ REF is the reference voltage allowable error; Step 4: collect data of the analog signal obtained in step 2, determine whether the working power supply of analog-to-digital conversion circuit B is normal through the collection results of the analog power supply and reference voltage of analog-to-digital conversion circuit B collected by analog-to-digital conversion circuit A, and set the normal or not flag bADPwrOK_B; determine whether the working power supply of analog-to-digital conversion circuit A is normal through the collection results of the analog power supply and reference voltage of analog-to-digital conversion circuit A collected by analog-to-digital conversion circuit B, and set the normal or not flag bADPwrOK_A; Step 5: judging and setting the normality flags bADOK_A and bADOK_B of the analog-to-digital conversion circuit A and the analog-to-digital conversion circuit B according to the bSampOK_A, bSampOK_B, bADPwrOK_A, and bADPwrOK_B status flags determined in step 3 and step 4; Step 6: for the analog signal acquisition data obtained in step 2, according to the acquisition results of the power supply sampling signals of the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B, determine whether the power supply of the signal sampling and conditioning circuit A and the signal sampling and conditioning circuit B is normal or not, bAIPwrOK_A and bAIPwrOK_B; Step 7: For the flags bADOK_A, bADOK_B and bAIPwrOK_A, bAIPwrOK_B determined in step 5 and step 6, determine whether the hardware working status of the signal sampling and acquisition circuit A and the signal sampling and acquisition circuit B is normal or not, flags bHardwareOK_A and bHardwareOK_B according to the following judgment logic: Step 8: for the external transmitter analog signal acquisition data obtained in step 2 and the flags bHardwareOK_A and bHardwareOK_B determined in step 7, determine the states bSigOK_Am and bSigOK_Bm of the m-th analog input signal acquired by the signal sampling and acquisition circuit A and the signal sampling and acquisition circuit B according to the following judgment logic: Where n is A or B, m=0, 1, 2, ... represents the m+1th analog input signal, V SIG_nm is the voltage value of the mth analog input signal collected by the first signal sampling and acquisition circuit 2A or the second signal sampling and acquisition circuit 2B, V SIG_mLowest and V SIG_mHighest They are the lower limit and upper limit of the m+1th analog input signal value respectively; Step 9: According to the final analog signal sampling value of the analog input signal status flags bSigOK_Am and bSigOK_Bm determined in step 8, if bSigOK_Am=TRUE, bSigOK_Bm=TRUE, then the analog signal sampling output: Determine the final signal sampling value according to the analog input selection logic configured by the functional safety software; if bSigOK_Am=TRUE, bSigOK_Bm=FALSE, then the analog signal sampling output is V SIG_Am ; If bSigOK_Am=FALSE、bSigOK_Bm=TRUE, the analog signal sampling output is V SIG_Bm ; If bSigOK_Am=FALSE, bSigOK_Bm=FALSE, the analog signal sampling output is: if the speed controller is in standby state, an alarm is issued and the speed controller is prohibited from starting; if the speed controller is in running state, an alarm is issued and the sampling value in the previous normal state is taken as the final sampling value or the controller is shut down directly according to the configuration of the functional safety software.

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