Circuit and chip for preventing false triggering

By introducing a replicated power regulator and static load into the SOC chip, the problem of false triggering of the power-on reset circuit is solved, ensuring normal chip operation and preventing erroneous signals caused by glitches.

CN115549023BActive Publication Date: 2026-08-283PEAK INC
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Patent Information

Application Number
CN202211287424.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-20
Publication Date
2026-08-28
Estimated Expiration
2042-10-20

AI Technical Summary

Technical Problem

When a large-scale SOC chip is powered on, the output voltage of the internal low-dropout regulator will glitch due to the simultaneous start-up of multiple clock domain circuits. This will cause the power-on reset circuit to be falsely triggered, outputting incorrect and invalid control signals and disrupting the normal operation of the chip.

Method used

By replicating the first power regulator, a second power regulator and a static load are added. By monitoring the switching between the first and second output voltages, the power-on reset circuit is ensured to operate in a stable state, thus avoiding false triggering.

Benefits of technology

It effectively prevents the power-on reset circuit from being falsely triggered due to load fluctuations in the main circuit, ensuring the normal operation of the chip and avoiding erroneous signal output caused by glitches.

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Abstract

The application discloses a circuit and a chip for preventing mis-triggering, which comprises a first power regulator, a main circuit load, a second power regulator, a static load and a control circuit. The first power regulator and the second power regulator are connected with a power-on reset circuit; the static load is connected with the power-on reset circuit; and the control circuit is connected with the power-on reset circuit, the first power regulator and the main circuit load. The circuit for preventing mis-triggering of the application adopts the mode of copying the first power regulator to obtain the second power regulator and the static load without jump, and the power-on reset circuit switches from monitoring the first output voltage and the second output voltage simultaneously to monitoring only the second output voltage from the power-on process to the completion of the power-on, which effectively reflects the power voltage change of the main circuit load and avoids the mis-triggering problem of the power-on reset circuit caused by the glitch of the main circuit load jump.
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