Ferroelectric device and method of manufacturing the same

By using a ferroelectric SOI dual-gate CMOS device structure, the top gate electrode and bottom gate electrode are separated, solving the problems of narrowing storage window and bias mismatch in the miniaturization process of ferroelectric transistors, and realizing low power consumption, high speed and high reliability in-memory operation.

CN118522733BActive Publication Date: 2026-01-23INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD +1
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Patent Information

Application Number
CN202410575830.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-05-10
Publication Date
2026-01-23
Estimated Expiration
2044-05-10

AI Technical Summary

Technical Problem

The classic von Neumann architecture faces the memory wall and power wall problems under the computing power requirements of big data and artificial intelligence. When the device size of ferroelectric transistors is miniaturized, the number of effective flip-domains decreases and the memory window narrows. The mismatch between the bias voltage for logic operations and changes in ferroelectric polarization states leads to the degradation of device performance.

Method used

A ferroelectric SOI dual-gate CMOS device structure is adopted. By separating the top gate electrode and the bottom gate electrode and applying different bias voltages to them respectively, the BOX layer is ferroelectricized in combination with SOI wafer process to achieve device separation. The ferroelectric layer is crystallized before fabrication to avoid thermal interference.

Benefits of technology

It achieves low power consumption, high computing speed and high reliability, and is suitable for heterogeneous integration and stacked packaging, solving the problems of device performance degradation and reliability.

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Abstract

The present disclosure provides a ferroelectric device and a preparation method thereof, which can be applied to the technical field of semiconductors. The ferroelectric device comprises a substrate layer; a bottom gate electrode located in the substrate layer; a ferroelectric layer located in the ferroelectric device, a lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer surrounding the ferroelectric layer; a channel layer in contact with an upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, all of which are in contact with an upper surface of the channel layer; a second device isolation layer between the source electrode, the drain electrode and the top gate electrode; and a stop layer between the first device isolation layer and the second device isolation layer, and surrounding the source electrode, the drain electrode and the top gate electrode.
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