Common-gate pixel driving circuit

Abstract

The invention discloses a common-gate pixel driving circuit which comprises a pre-storage module and a driving module, the pre-storage module comprises a first transistor and a second transistor, a first source drain electrode of the first transistor is coupled to a data signal line, a second source drain electrode of the first transistor is coupled to a pre-storage capacitor and the second transistor, and a second source drain electrode of the second transistor is coupled to a data signal line. The grid electrode is coupled to a control signal line; a gate of the second transistor is coupled to a transfer signal line; the driving module comprises a third transistor and a fourth transistor, a first source drain electrode of the third transistor is coupled to a first global signal, and a second source drain electrode of the third transistor is coupled to a pixel capacitor; a first source drain electrode of the fourth transistor is coupled to a second global signal, and a second source drain electrode of the fourth transistor is coupled to the pixel capacitor; grid electrodes of the third transistor and the fourth transistor are coupled to a second source drain electrode of the second transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel driving, and in particular to a common-gate pixel driving circuit. Background Art

[0002] In traditional field sequential or color sequential display driving technology, the backlight can only be turned on after all screen data is written and the liquid crystal is deflected to a stable state, otherwise the screen will be chaotic. Therefore, the data writing and liquid crystal deflection time will greatly compress the backlight turn-on time, resulting in difficulties in improving the brightness of the display, as well as difficulties in improving the refresh rate and resolution, increased power consumption and increased backlight material costs. Therefore, how to speed up the liquid crystal driving time and increase the backlight turn-on time is a very important issue.

[0003] For the circuit of gate control driving structure, its storage capacitance requirement is smaller than that of charge sharing or conventional traditional LCD pixel driving circuit. Taking the traditional display circuit as an example, Cst is at least of the same order of magnitude as Clc, and in some high refresh products, it is even dozens of times of Clc. Since the size of Clc is related to the deflection of liquid crystal, which is related to the voltage, and the response of liquid crystal takes time, the shorter the charging time, the less time Clc has to react to the target potential capacitance, and Cst is required to continuously power it.

[0004] For the circuit of the gate control driving structure, the data capacitor is stored in the gate signal of the driving transistor Vg=Vdata. When Vpixel<Vdata, and Vg-Vpixel>Vth, a channel is formed. The gate-controlled driving transistor operates in the saturation region. For NMOS, Vdg=Vdd-Vg>Vth. At this time, for Vpixel, electrons will flow from Vpixle to Vdd, gradually raising the potential of Vpixel until it reaches a balance state close to Vgs=Vth, Vdg>Vth. Because if electrons continue to flow out at this time, Vs will increase the potential, Vgs<Vth, and the device channel will be pinched off. In addition, it can be seen from the above driving process that the target charging potential is only related to the gate signal potential and has nothing to do with the gate signal capacitance. Therefore, the gate signal capacitance can be made very small, which is conducive to the improvement of the aperture ratio. However, it also has fatal shortcomings. For NMOS, the previous frame signal is a negative frame voltage and the next frame is a positive frame voltage, which can satisfy the state of Vgs>Vth. However, for the opposite situation, the previous frame is a positive frame voltage and the next frame is a negative frame voltage, Vgs<Vth, the channel cannot be opened, and the same gate drive process cannot be achieved.

[0005] Even if Vpixel is set to Vd in the driving process, the discharge logic is used to set Vdd to a low potential, satisfying Vg-Vdd>Vth to open the channel. As electrons flow into Vpixel, the potential of Vpixel continues to decrease to Vpixle-Vg=Vth. However, since the channel still exists, electrons will continue to flow into Vpixel, and the potential will continue to decrease to Vdd. Therefore, how to ensure the polarity reversal of liquid crystal under gate control is the limitation of gate control scheme in liquid crystal application.

[0006] In summary, the conventional gate-controlled pixel driving circuit has the problem of being unable to reverse the polarity of liquid crystal. Summary of the invention

[0007] In view of this, the present invention provides a common-gate pixel driving circuit, which solves the problem that the conventional gate-controlled pixel driving circuit cannot perform liquid crystal polarity inversion by improving the circuit structure and driving timing.

[0008] To solve the above problems, the technical solution of the present invention is to adopt a common-gate pixel driving circuit, including: a pre-storage module and a driving module, wherein the pre-storage module includes a first transistor and a second transistor, the first source and drain of the first transistor are coupled to the data signal line, the second source and drain are coupled to the pre-storage capacitor and the second transistor, and the gate is coupled to the control signal line; the gate of the second transistor is coupled to the transfer signal line; the driving module includes a third transistor and a fourth transistor, the first source and drain of the third transistor are coupled to the first global signal, and the second source and drain are coupled to the pixel capacitor; the first source and drain of the fourth transistor are coupled to the second global signal, and the second source and drain are coupled to the pixel capacitor; the gates of the third transistor and the fourth transistor are both coupled to the second source and drain of the second transistor.

[0009] Optionally, when the third transistor is an N-type MOS tube and the fourth transistor is a P-type MOS tube, the second source and drain of the third transistor and the fourth transistor are both coupled to the same end of the pixel capacitor, and the other end of the pixel capacitor is coupled to a common signal line.

[0010] Optionally, the third transistor and the fourth transistor can also be configured as dual-gate transistors.

[0011] Optionally, the second gate of the third transistor is coupled to the first reference signal line and the second gate of the fourth transistor is coupled to the second reference signal line, wherein the second source and drain of the third transistor are both coupled to one end of the pixel capacitor, and the second source and drain of the fourth transistor are both coupled to the other end of the pixel capacitor.

[0012] Optionally, the second gate of the third transistor is coupled to a second global signal and the second gate of the fourth transistor is coupled to a first global signal, wherein the second source and drain of the third transistor are both coupled to one end of the pixel capacitor, and the second source and drain of the fourth transistor are both coupled to the other end of the pixel capacitor.

[0013] Optionally, one end of the pre-storage capacitor away from the transistor is coupled to a common signal line.

[0014] Optionally, the pixel driving circuit also includes a reset module, the reset module includes a fifth transistor, the first source and drain of the fifth transistor are coupled to the common signal, the second source and drain are coupled to the gates of the third transistor and the fourth transistor, and the gate is coupled to the reset signal line.

[0015] Optionally, in the positive polarity frame: in the backlight-on stage, the control signal jumps to a high potential, the first transistor is turned on, and the data signal is stored in the pre-storage capacitor; in the backlight-off stage, the transfer signal jumps to a high potential, the second global signal and the first global signal jump to a high potential successively, and the data signal is transmitted to the gates of the third transistor and the fourth transistor. At this time, the third transistor is turned on and the fourth transistor remains off, so that the positive polarity data signal is transmitted to the pixel capacitor through the third transistor.

[0016] Optionally, in the negative polarity frame: in the backlight-on stage, the control signal jumps to a high potential, the first transistor is turned on, and the data signal is stored in the pre-storage capacitor; in the backlight-off stage, the transfer signal jumps to a high potential, the first global signal and the second global signal jump to a low potential successively, and the data signal is transmitted to the gates of the third transistor and the fourth transistor. At this time, the third transistor is turned off and the fourth transistor is turned on, so that the negative polarity data signal is transmitted to the pixel capacitor through the fourth transistor.

[0017] The primary improvement of the present invention is the common-gate pixel driving circuit provided. By setting a pre-storage capacitor in cooperation with the transistor, the grayscale voltage of the next frame is stored by the pre-storage capacitor during the backlight emission time of the current frame, so that all pixels can synchronously realize the grayscale voltage when the backlight is turned off, which greatly reduces the writing time of the pixel voltage and relatively increases the backlight emission time.

[0018] At the same time, the present invention achieves a smaller capacitor area ratio through a common gate by coupling the gates of the third transistor and the fourth transistor to the second source and drain of the second transistor, and achieves voltage reversal across the liquid crystal capacitor with the frame, thereby solving the problem of the inability to reverse the polarity of the liquid crystal in the traditional gate-controlled pixel driving circuit and avoiding the liquid crystal polarization problem.

[0019] Furthermore, by cooperating with the third transistor and the fourth transistor, only one of the third transistor and the fourth transistor is in the on working state in any frame, thereby reducing the rate of transistor threshold voltage drift and improving the accuracy of grayscale control of the pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 1 of the present invention; Figure 2 is a simplified driving timing diagram of the pixel driving circuit of Embodiment 1 of the present invention; Figure 3 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 2 of the present invention; Figure 4 is a simplified driving timing diagram of a pixel driving circuit according to Embodiment 2 of the present invention; Figure 5 is a simplified circuit diagram of a pixel driving circuit according to Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0022] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0024] The following embodiments of the technical solution of the present application are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, and are therefore only used as examples, and cannot be used to limit the scope of protection of the present application.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.

[0026] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0027] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0028] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. Example 1

[0029] Specifically, Figure 1 As shown, a common-gate pixel driving circuit includes: a pre-storage module and a driving module, wherein the pre-storage module includes a first transistor M1 and a second transistor M2, the first source and drain of the first transistor M1 are coupled to the data signal line Data, the second source and drain are coupled to the pre-storage capacitor Cst, and the second transistor M2 has a gate coupled to the control signal line Scan; the gate of the second transistor M2 is coupled to the transfer signal line Tran; the driving module includes a third transistor M3 and a fourth transistor M4, the first source and drain of the third transistor M3 are coupled to the first global signal Vdd1, and the second source and drain are coupled to the pixel capacitor Clc; the first source and drain of the fourth transistor M4 are coupled to the second global signal Vdd2, and the second source and drain are coupled to the pixel capacitor Clc; the gates of the third transistor M3 and the fourth transistor M4 are both coupled to the second source and drain of the second transistor M2.

[0030] Further, when the third transistor M3 is an N-type MOS tube and the fourth transistor M4 is a P-type MOS tube, the second source and drain of the third transistor M3 and the fourth transistor M4 are coupled to the same end of the pixel capacitor Clc, and the other end of the pixel capacitor Clc is coupled to the common signal line Com.

[0031] Furthermore, one end of the pre-storage capacitor Cst away from the transistor is coupled to the common signal line Com.

[0032] Specifically, Figure 2 As shown, the driving timing of the pixel driving circuit is configured as follows: In the first frame of positive polarity, in the backlight-on stage, the control signal jumps to a high potential row by row, the first transistor M1 is turned on, and the data signal is stored in the pre-storage capacitor Cst; in the backlight-off stage, the transfer signal jumps to a high potential, the second global signal and the first global signal jump to a high potential successively, and the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4. At this time, the third transistor M3 is turned on and the fourth transistor M4 remains turned off, so that the positive polarity data signal is transmitted to the pixel capacitor Cst through the third transistor M3.

[0033] In the second frame of negative polarity, during the backlight-on stage, the control signal jumps to a high potential, the first transistor M1 is turned on, and the data signal is stored in the pre-storage capacitor Cst; during the backlight-off stage, the transfer signal jumps to a high potential, the first global signal and the second global signal successively jump to a low potential, and the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4. At this time, the third transistor M3 is turned off and the fourth transistor M4 is turned on, so that the negative polarity data signal is transmitted to the pixel capacitor Cst through the fourth transistor M4.

[0034] Furthermore, the high potential of the control signal and the transfer signal is defined as a potential that can turn on the transistor, and the low potential of the control signal and the transfer signal is defined as a potential that can turn off the transistor; the high potential of the first global signal is defined as a potential higher than Vop-max (maximum grayscale voltage), and the low potential is defined as the same as the common signal Com; the high potential of the second global signal is defined as the same as the common signal Com, and the low potential is defined as a potential lower than -Vop-max.

[0035] Furthermore, the pixel driving circuit also includes a reset module, which includes a fifth transistor M5, a first source and drain of the fifth transistor M5 coupled to the common signal Com, a second source and drain coupled to the gates of the third transistor M3 and the fourth transistor M4, and a gate coupled to the reset signal line Reset.

[0036] Specifically, in the case where the pixel driving circuit is provided with a reset module, the driving timing of the pixel driving circuit also includes: in the backlight off stage, the reset signal is first jumped to a high potential to turn on the fifth transistor, so that the potential of the gate of the third transistor M3 and the fourth transistor M4 is reset based on the common signal, and then the reset signal jumps to a low potential, and then the transfer signal jumps.

[0037] The present invention sets a pre-storage capacitor to cooperate with the transistor, so that during the backlight emitting time of the current frame, the grayscale voltage of the next frame is stored by the pre-storage capacitor, so that all pixels can synchronously realize the grayscale voltage when the backlight is turned off, which greatly reduces the writing time of the pixel voltage and relatively increases the backlight emitting time. At the same time, the present invention achieves a smaller capacitor area ratio by coupling the gates of the third transistor and the fourth transistor to the second source and drain of the second transistor through the common gate, and realizes the voltage at both ends of the liquid crystal capacitor to reverse with the frame, which solves the problem that the traditional gate-controlled pixel driving circuit cannot reverse the polarity of the liquid crystal and avoids the liquid crystal polarization problem. In addition, by cooperating with the third transistor and the fourth transistor, it is achieved that only one of the third transistor and the fourth transistor is in the on working state in any frame, thereby reducing the rate of transistor threshold voltage drift and improving the accuracy of grayscale control of the pixel driving circuit. Example 2

[0038] like Figure 3 As shown, the third transistor M3 and the fourth transistor M4 can also be configured as dual-gate transistors.

[0039] Further, the second gate of the third transistor M3 is coupled to the first reference signal line Ref1 and the second gate of the fourth transistor M4 is coupled to the second reference signal line Ref2, wherein the second source and drain of the third transistor M3 are both coupled to one end of the pixel capacitor Clc, and the second source and drain of the fourth transistor M4 are both coupled to the other end of the pixel capacitor Clc.

[0040] Furthermore, Figure 4 As shown, the driving timing of the pixel driving circuit is configured as follows: In the first frame, during the backlight-on stage, the control signal jumps to a high potential row by row, the first transistor M1 is turned on, and the data signal is stored in the pre-storage capacitor Cst; during the backlight-off stage, the transfer signal jumps to a high potential, the first global signal and the second reference signal jump to a high potential, and the second global signal and the first reference signal jump to a normal potential. When the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4, due to the effect of the reference signal, the Vth of the third transistor remains unchanged and the Vth of the fourth transistor is reduced, so that the third transistor M3 works in the saturation region and the fourth transistor works in the linear region, and then the data signal is transmitted to one end of the pixel capacitor Cst through the third transistor M3, and the common signal is transmitted to the other end of the pixel capacitor Cst through the fourth transistor M4, thereby completing the grayscale control of the pixel capacitor in the positive frame.

[0041] In the second frame, during the backlight-on stage, the control signal jumps to a high potential row by row, the first transistor M1 is turned on, and the data signal is stored in the pre-storage capacitor Cst; during the backlight-off stage, the transfer signal jumps to a high potential, the first global signal and the second reference signal jump to a normal potential, and the second global signal and the first reference signal jump to a high potential. When the data signal is transmitted to the gates of the third transistor M3 and the fourth transistor M4, due to the effect of the reference signal, the Vth of the fourth transistor remains unchanged and the Vth of the third transistor is reduced, so that the third transistor M3 works in the linear region and the fourth transistor works in the saturation region, and then the common signal is transmitted to one end of the pixel capacitor Cst through the third transistor M3, and the data signal is transmitted to the other end of the pixel capacitor Cst through the fourth transistor M4, thereby completing the grayscale control of the negative frame of the pixel capacitor.

[0042] Furthermore, the high potential of the first global signal, the second global signal, the first reference signal and the second reference signal involved in this embodiment is a potential higher than Vop-max (maximum grayscale voltage), and the normal potential is the same as the common signal Com.

[0043] This embodiment achieves a lower Data Range and higher working state stability by switching pixel electrodes, avoiding the problem that when the fourth transistor M4 adopts PMOS (such as LTPS process), a higher leakage current may exist in the off state, which will cause Vpixel to deviate more and more from the target charging level when the circuit refresh rate is lower.

[0044] Furthermore, the pixel driving circuit also includes a reset module, which includes a fifth transistor M5, a first source and drain of the fifth transistor M5 coupled to the common signal Com, a second source and drain coupled to the gates of the third transistor M3 and the fourth transistor M4, and a gate coupled to the reset signal line Reset. Example 3

[0045] like Figure 5 As shown, the third transistor M3 and the fourth transistor M4 can also be configured as dual-gate transistors.

[0046] Further, the second gate of the third transistor M3 is coupled to the second global signal Vdd2 and the second gate of the fourth transistor M4 is coupled to the first global signal Vdd1, wherein the second source and drain of the third transistor M3 are both coupled to one end of the pixel capacitor Clc, and the second source and drain of the fourth transistor M4 are both coupled to the other end of the pixel capacitor Clc.

[0047] Furthermore, the driving timing of this embodiment is similar to the driving timing of Embodiment 2, and thus will not be described in detail.

[0048] Compared with Example 2, this embodiment further improves the aperture ratio by merging the Vref and Vdd signal lines. At the same time, due to the removal of the fifth transistor M5 and the corresponding signal line, the size of Cst1 can be appropriately increased, so that the capacitance ratio of Cst1 / Cst2 is 2-3 orders of magnitude different, and the voltage loss can be basically ignored.

[0049] The above is a common-gate pixel driving circuit provided in an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0050] Professionals may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented with a software module executed by a hardware or processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the technical field.

Claims

1. A common-gate pixel driving circuit, characterized in that: include: A pre-storage module and a drive module, wherein: The pre-storage module comprises a first transistor (M1) and a second transistor (M2), wherein a first source and a drain of the first transistor (M1) are coupled to a data signal line (Data), a second source and a drain of the first transistor (M1) are coupled to a pre-storage capacitor (Cst) and the second transistor (M2), and a gate of the first transistor (M2) is coupled to a control signal line (Scan); and a gate of the second transistor (M2) is coupled to a transfer signal line (Tran); The driving module comprises a third transistor (M3) and a fourth transistor (M4), wherein a first source and a drain of the third transistor (M3) are coupled to a first global signal (Vdd1), and a second source and a drain of the third transistor (M3) are coupled to a pixel capacitor (Clc); a first source and a drain of the fourth transistor (M4) are coupled to a second global signal (Vdd2), and a second source and a drain of the fourth transistor (M4) are coupled to the pixel capacitor (Clc); The gates of the third transistor (M3) and the fourth transistor (M4) are both coupled to the second source and drain of the second transistor (M2).

2. The pixel driving circuit according to claim 1, characterized in that: When the third transistor (M3) is an N-type MOS transistor and the fourth transistor (M4) is a P-type MOS transistor, The second source and drain of the third transistor (M3) and the fourth transistor (M4) are both coupled to the same end of the pixel capacitor (Clc), and the other end of the pixel capacitor (Clc) is coupled to a common signal line (Com).

3. The pixel driving circuit according to claim 1, characterized in that: The third transistor (M3) and the fourth transistor (M4) can also both be configured as dual-gate transistors.

4. The pixel driving circuit according to claim 3, characterized in that: The second gate of the third transistor (M3) is coupled to the first reference signal line (Ref1) and the second gate of the fourth transistor (M4) is coupled to the second reference signal line (Ref2), wherein, The second source and drain of the third transistor (M3) are both coupled to one end of the pixel capacitor (Clc), and the second source and drain of the fourth transistor (M4) are both coupled to the other end of the pixel capacitor (Clc).

5. The pixel driving circuit according to claim 3, characterized in that: The second gate of the third transistor (M3) is coupled to the second global signal (Vdd2) and the second gate of the fourth transistor (M4) is coupled to the first global signal (Vdd1), wherein, The second source and drain of the third transistor (M3) are both coupled to one end of the pixel capacitor (Clc), and the second source and drain of the fourth transistor (M4) are both coupled to the other end of the pixel capacitor (Clc).

6. The pixel driving circuit according to claim 1, characterized in that: One end of the pre-storage capacitor (Cst) away from the transistor is coupled to the common signal line (Com).

7. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes a reset module. The reset module comprises a fifth transistor (M5), a first source and a drain of the fifth transistor (M5) coupled to a common signal (Com), a second source and a drain coupled to gates of the third transistor (M3) and the fourth transistor (M4), and a gate coupled to a reset signal line (Reset).

8. The pixel driving circuit according to claim 2, characterized in that: In positive polarity frame: In the backlight on stage, the control signal jumps to a high potential, the first transistor (M1) is turned on, and after the data signal is stored in the pre-storage capacitor (Cst), the control signal jumps back to a low potential; In the backlight off stage, the transfer signal jumps to a high potential, the second global signal and the first global signal jump to a high potential successively, and the data signal is transmitted to the gates of the third transistor (M3) and the fourth transistor (M4). At this time, the third transistor (M3) is turned on and the fourth transistor (M4) remains turned off, so that the positive polarity data signal is transmitted to the pixel capacitor (Cst) through the third transistor (M3).

9. The pixel driving circuit according to claim 8, characterized in that: In negative polarity frame: In the backlight-on stage, the control signal jumps to a high potential, the first transistor (M1) is turned on, and the data signal is stored in the pre-storage capacitor (Cst); In the backlight off stage, the transfer signal jumps to a high potential, the first global signal and the second global signal jump to a low potential successively, and the data signal is transmitted to the gates of the third transistor (M3) and the fourth transistor (M4). At this time, the third transistor (M3) is turned off and the fourth transistor (M4) is turned on, so that the negative polarity data signal is transmitted to the pixel capacitor (Cst) through the fourth transistor (M4).

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