Nano laminated structure thin film with multi-resistance-state non-volatility and preparation method and application of nano laminated structure thin film

Abstract

The invention provides a nano laminated structure film with multi-resistance-state non-volatility and a preparation method and application thereof, and belongs to the technical field of microelectronic materials. The novel superlattice-like Ge2Sb2Te5 / Sb7Se3 thin film is formed by constructing a nano laminated structure, complementary advantages of the Ge2Sb2Te5 and the Sb7Se3 thin film are achieved, and the phase change performance of the thin film is regulated and controlled by regulating and controlling the thickness ratio, the interface number, the total thickness and other structural parameters of the Ge2Sb2Te5 thin film and the Sb7Se3 thin film. Multi-configuration and non-volatile information storage is realized by using a stress effect and an interface effect existing between layers in the nano laminated structure. Meanwhile, the existence of the interface can induce the phase change material to accelerate crystallization and generate phonon scattering, so that the phase change speed is improved, and the heat conductivity and the RESET operation power consumption are reduced. The nano laminated structure thin film with the multi-resistance-state non-volatility can be widely applied to big data mass storage and neuromorphic calculation in 5G, Internet of Things, cloud computing and artificial intelligence times.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic materials, and in particular to a nano-laminated structure film with multi-resistance state non-volatility and a preparation method and application thereof. Background Art

[0002] In 1968, Stanford R. Ovshinsky discovered that chalcogenides have reversible phase change properties. In 2015, Intel and Micron jointly developed 3D-Xpoint technology based on phase change storage. In 2021, Wang proposed phase change storage technology for neural computing. In 2022, He discovered all-dielectric phase change materials for low-loss, ultra-fast all-optical switching. In 2023, Kim studied XTe2 / Ta with excellent thermal stability and device performance. x Sb2Te3 phase change memory material.

[0003] At present, the most widely studied phase change materials are composed of Ge, Sb, Te and other elements. These elements can produce surprising effects when combined in a specific proportion. The most representative phase change material is Ge2Sb2Te5 (GST for short). However, its phase change temperature T c About 157℃, ten-year data retention temperature T 10 It is only 78℃, which is far from meeting the requirements of 120℃ and 150℃ in the fields of automotive electronics, aerospace electronics, etc. At the same time, the melting point of GST material T m As high as 620℃, which means it has a large operating power consumption. In addition, the density change rate of GST material before and after phase change is as high as 8.8%, the stress is large and the grain size reaches hundreds of nanometers, which damages the reliability and stability of storage devices. In order to make up for the above-mentioned defects in the phase change performance of GST materials, researchers have developed new composite phase change materials by doping, such as doping Ti, Se, Sn, Ni and other elements, but still cannot obtain more ideal phase change performance, including crystallization temperature, phase change speed, amorphous thermal stability, crystalline resistance, density change rate, fatigue characteristics, etc.

[0004] In recent years, Wu et al. found that Ti-Sb-Se phase change material contains Se element, which has the characteristics of high crystallization temperature, fast phase change speed, low melting point and thermal conductivity, suitable high and low resistance difference, etc. It has outstanding advantages in thermal stability, data retention and power consumption, making it a ternary nano phase change material with good performance. However, the amorphous high resistance of the phase change material is relatively high. After being prepared into a device, under the action of a voltage pulse, the high RESET state resistance makes the device SET operation difficult to achieve. Moreover, the ratio of amorphous and crystalline resistance is large, which is due to the large change in atomic structure. Large structural changes will cause large changes in density and internal stress, thereby reducing the cycle life of the device. In addition, Ti-Sb-Se phase change material has only two storage states, high resistance and low resistance, and cannot realize large data storage. Summary of the invention

[0005] The purpose of the present invention is to provide a nano-laminated structure film with multi-resistance non-volatility and a preparation method and application thereof, which can be widely used in big data mass storage and neuromorphic computing in the era of 5G, Internet of Things, cloud computing, and artificial intelligence.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] The present invention provides a nano-laminated structure film with multi-resistance state non-volatility, wherein the nano-laminated structure film with multi-resistance state non-volatility is a Ge2Sb2Te5 / Sb7Se3 film, comprising a stacked Ge2Sb2Te5 film and a Sb7Se3 film; the total thickness of the Ge2Sb2Te5 / Sb7Se3 film is 60nm, and the general structural formula is Ge2Sb2Te5(x nm) / Sb7Se3(60-x nm), wherein x represents the thickness of the Ge2Sb2Te5 film, and 0 <x<60。

[0008] Furthermore, the structure of the nano-laminated structure film with multi-resistance non-volatility is one of Ge2Sb2Te5 (5nm) / Sb7Se3 (55nm), Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm), Ge2Sb2Te5 (15nm) / Sb7Se3 (45nm), Ge2Sb2Te5 (20nm) / Sb7Se3 (40nm), and Ge2Sb2Te5 (35nm) / Sb7Se3 (25nm).

[0009] The present invention also provides a method for preparing the above-mentioned nano-laminated structure film with multi-resistance non-volatility, characterized in that it comprises the following steps:

[0010] (1) taking a single crystal P-type 100 oriented silicon wafer, splitting, cleaning, and drying to obtain a dried single crystal P-type 100 oriented silicon wafer;

[0011] (2) Take the dried single crystal P-type 100-oriented silicon wafer, install Ge2Sb2Te5 and Sb7Se3 targets, and evacuate;

[0012] (3) Adjust the sputtering gas argon flow rate, vacuum chamber sputtering pressure, target sputtering power, adjust the gate valve to control the pressure in the chamber, start the sputtering power supply of Ge2Sb2Te5 and Sb7Se3 targets, and perform pre-sputtering;

[0013] (4) Turn on the sample turntable to rotate the single crystal P-type 100-oriented silicon wafer at a constant speed, and rotate to the Ge2Sb2Te5 target position to sputter the Ge2Sb2Te5 film. After the sputtering of the Ge2Sb2Te5 film is completed, rotate to the Sb7Se3 target position to sputter the Sb7Se3 film, thereby obtaining a nano-laminated structure film with multi-resistance non-volatility.

[0014] Furthermore, the segmentation in step (1) is to divide the single crystal P-type 100 oriented silicon wafer into The cleaning step comprises:

[0015] a. Place the cut single crystal P-type 100 oriented silicon wafer in an acetone solution for ultrasonic cleaning for 5 to 10 minutes, and then rinse with deionized water;

[0016] b. Then put it in alcohol for ultrasonic cleaning for 5 to 10 minutes, and rinse with deionized water after the ultrasonic cleaning;

[0017] c. Then place it in a quartz container filled with H2O2 + ammonia solution and heat until it boils, then rinse with deionized water;

[0018] d. Put it into H2O2+HCl solution and boil it, boil and clean it for 5 to 10 minutes, and rinse it with deionized water.

[0019] Furthermore, the vacuum degree of the vacuum in step (2) is ≤2.0×10 -4 Pa.

[0020] Furthermore, in step (3), the sputtering gas argon flow rate is 30-50 SCCM; the target sputtering power is 20-30 W; the gas pressure in the chamber is adjusted to 2-4×10 -1 Pa; the pre-sputtering time is 50 to 60 seconds.

[0021] Furthermore, in step (4), the uniform rotation speed of the single crystal P-type 100-oriented silicon wafer is 15 to 35 rpm; the sputtering speed of the Ge2Sb2Te5 target is 2.4 to 2.5 s / nm; and the sputtering speed of the Sb7Se3 target is 2.2 to 2.3 s / nm.

[0022] The present invention also provides an application of the above-mentioned multi-resistance non-volatile nano-laminated structure film as a phase change memory film in neuromorphic computing or large-capacity data storage.

[0023] In order to overcome the defects of the individual phase change materials of Ge2Sb2Te5 and Sb7Se3, the present invention forms a new type of superlattice-like Ge2Sb2Te5 / Sb7Se3 thin film material by constructing a nano-laminated structure, so as to achieve complementary advantages between the two, and regulate the film phase change performance by regulating the thickness ratio, number of interfaces, total thickness and other structural parameters of the Ge2Sb2Te5 and Sb7Se3 thin films, and utilize the stress effect and interface effect between layers in the nano-laminated structure to achieve multi-configuration and non-volatile information storage. At the same time, the presence of the interface will induce the phase change material to accelerate crystallization and produce phonon scattering, thereby achieving an increase in the phase change speed, a reduction in thermal conductivity and RESET operation power consumption. The new nano-laminated structure Ge2Sb2Te5 / Sb7Se3 thin film can be widely used in 5G, Internet of Things, cloud computing, and big data mass storage and neuromorphic computing in the era of artificial intelligence.

[0024] Compared with the traditional phase change material Ge2Sb2Te5, the nano-laminated structure Ge2Sb2Te5 (x nm) / Sb7Se3 (60-x nm) film prepared by the present invention has many advantages:

[0025] First, the nano-laminated structure Ge2Sb2Te5(x nm) / Sb7Se3(60-x nm) film underwent two successive phase transition processes, with obvious high-resistance state, intermediate state, and low-resistance state, demonstrating the novelty and non-volatility of multi-state storage.

[0026] Second, the phase change temperature, crystallization activation energy, and data retention of the nano-laminated structure Ge2Sb2Te5 (x nm) / Sb7Se3 (60-x nm) film are higher than those of the single-layer Ge2Sb2Te5 phase change material, showing excellent amorphous thermal stability.

[0027] Third, the phase transition temperature and resistance of the nano-laminated Ge2Sb2Te5 (x nm) / Sb7Se3 (60-x nm) film can be controlled by adjusting parameters such as the total thickness, number of interfaces and thickness ratio of the laminated structure.

[0028] Fourth, the Sb7Se3 layer in the nano-laminated structure Ge2Sb2Te5(x nm) / Sb7Se3(60-x nm) film is rich in Sb element. At the same time, due to the existence of the interface, the Ge2Sb2Te5(x nm) / Sb7Se3(60-x nm) film has a nanosecond phase transition speed.

[0029] Fifth, the existence of the interface in the nano-laminated structure Ge2Sb2Te5 (x nm) / Sb7Se3 (60-x nm) film reduces its thermal conductivity, greatly improving the heating efficiency of the film under the action of electric pulses, thereby reducing the operating power consumption of the film crystallization and amorphization.

[0030] Sixth, the nano-laminated structure Ge2Sb2Te5 (x nm) / Sb7Se3 (60-x nm) film has a lower density change before and after the phase change, which is conducive to the full contact between the phase change film and the upper and lower electrodes, ensuring the working reliability and cycle life of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Curves showing the relationship between the in-situ resistance and temperature of the multi-resistance non-volatile nano-laminated structures Ge2Sb2Te5(5nm) / Sb7Se3(55nm), Ge2Sb2Te5(10nm) / Sb7Se3(50nm), Ge2Sb2Te5(15nm) / Sb7Se3(45nm), Ge2Sb2Te5(20nm) / Sb7Se3(40nm), and Ge2Sb2Te5(35nm) / Sb7Se3(25nm) films prepared in Examples 1 to 5;

[0032] Figure 2 The curves showing the relationship between the in-situ resistance and temperature of the Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) film, 100nm single-layer Ge2Sb2Te5 film, and 100nm single-layer Sb7Se3 film prepared in Example 1, Comparative Example 1, and Comparative Example 2. DETAILED DESCRIPTION

[0033] The embodiments of the present invention are described in detail below, and the embodiments are intended to explain the present invention and should not be construed as limiting the present invention. If specific techniques or conditions are not specified in the embodiments, they are carried out according to the techniques or conditions described in the literature in this area or according to the product specifications. If the manufacturers of reagents or instruments are not specified, they are all conventional products that can be obtained commercially.

[0034] Example 1

[0035] Preparation of Ge2Sb2Te5(10nm) / Sb7Se3(50nm) Nano-Layered Thin Films with Multi-resistance Non-volatile Properties

[0036] (1) Slicing

[0037] A diamond knife is used to cut a single crystal P-type (100) oriented silicon wafer with a diameter of 100 mm and a thickness of 0.5 mm into Square pieces are prepared for physical vapor deposition, high temperature annealing, phase change performance testing and microstructure characterization of nano-laminated structure Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) films.

[0038] (2) Cleaning

[0039] The cut single crystal P-type (100) oriented silicon wafer was placed in an acetone solution for ultrasonic cleaning for 6 minutes, and then rinsed with deionized water; then placed in alcohol for ultrasonic cleaning for 6 minutes, and rinsed with deionized water after the ultrasonic cleaning; then placed in a quartz container filled with H2O2 + ammonia solution and heated until boiling, and then rinsed with deionized water; then placed in H2O2 + HCl solution and boiled, boiled and cleaned for 5 minutes, and rinsed with deionized water; finally, the sample was placed in an oven and dried at 120°C for about 20 minutes to obtain a dried single crystal P-type (100) oriented silicon wafer.

[0040] (3) Vacuuming

[0041] Install the sputtering target and the dried single crystal P-type (100) oriented silicon wafer, install the Ge2Sb2Te5 and Sb7Se3 targets, start the mechanical pump to roughly vacuum to 20Pa, and then start the molecular pump to finely vacuum to 2.0×10 -4 Pa.

[0042] (4) Sputtering

[0043] A. Set the sputtering gas argon flow rate to 30 SCCM, the vacuum chamber sputtering pressure to 2.5 Pa, and the target sputtering power to 30 W;

[0044] B. Adjust the gate valve to make the pressure in the chamber reach 4×10 -1 Pa, turn on the sputtering power supply of Ge2Sb2Te5 and Sb7Se3 targets, and pre-sputter for 60s;

[0045] C. Turn on the sample turntable to rotate the dried single crystal P-type (100) oriented silicon wafer at a speed of 20 rpm to ensure that a high-quality film with uniform thickness and composition is obtained;

[0046] D. Calculate the sputtering time according to the design requirements of the film thickness to prepare Ge2Sb2Te5 (5nm) / Sb7Se3 (55nm) thin film: first rotate the dried single crystal P-type (100) oriented silicon wafer to the Ge2Sb2Te5 target position, and sputter the Ge2Sb2Te5 film at a sputtering rate of 2.439s / nm. After the sputtering of the Ge2Sb2Te5 film is completed, turn off the Ge2Sb2Te5 sputtering power supply; then place the rotated single crystal P-type (100) oriented silicon wafer after sputtering to the Sb7Se3 target position, and sputter the Sb7Se3 film at a sputtering rate of 2.218s / nm. After the sputtering of the Sb7Se3 film is completed, turn off the Sb7Se3 sputtering power supply to obtain a Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) thin film.

[0047] Example 2

[0048] The same method for preparing a multi-resistance non-volatile nano-laminated structure film as in Example 1 was adopted, and the sputtering time was changed according to the thickness of the film to prepare a Ge2Sb2Te5 (5nm) / Sb7Se3 (55nm) film.

[0049] Example 3

[0050] The same method for preparing a multi-resistance non-volatile nano-laminated structure film as in Example 1 was adopted, and the sputtering time was changed according to the film thickness to prepare a Ge2Sb2Te5 (15nm) / Sb7Se3 (45nm) film.

[0051] Example 4

[0052] The same method for preparing a multi-resistance non-volatile nano-laminated structure film as in Example 1 was adopted, and the sputtering time was changed according to the film thickness to prepare a Ge2Sb2Te5 (20nm) / Sb7Se3 (40nm) film.

[0053] Example 5

[0054] The same method for preparing a multi-resistance non-volatile nano-laminated structure film as in Example 1 was adopted, and the sputtering time was changed according to the thickness of the film to prepare a Ge2Sb2Te5 (35nm) / Sb7Se3 (25nm) film.

[0055] The in-situ resistance of the Ge2Sb2Te5(x nm) / Sb7Se3(60-x nm) thin films prepared in Examples 1 to 5 at different temperatures was measured. The results are as follows: Figure 1 shown.

[0056] Depend on Figure 1It can be seen that as the annealing temperature continues to increase, the nano-laminated structure Ge2Sb2Te5 (5nm) / Sb7Se3 (55nm), Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm), Ge2Sb2Te5 (15nm) / Sb7Se3 (45nm), Ge2Sb2Te5 (20nm) / Sb7Se3 (40nm), Ge2Sb2Te5 (35nm) / Sb7Se3 (25nm) films all undergo two phase transition processes, and multi-configuration non-volatile storage can be achieved. The first step crystallization temperature T C1 As the thickness of the Ge2Sb2Te5 layer increases, the second step crystallization temperature T C2 It increases with the decrease of Sb7Se3 layer thickness, indicating that there are two opposite dependences of crystallization temperature on thickness in the stacked structure Ge2Sb2Te5 / Sb7Se3 film. The first resistance mutation is caused by the crystallization of Ge2Sb2Te5 film. The Raman shift of the phonon mode of Ge2Sb2Te5 layer increases with the decrease of thickness, that is, the stress of Ge2Sb2Te5 layer increases with the decrease of thickness. Stress has the effect of promoting crystallization, resulting in T C1 The second resistance mutation is caused by the crystallization of Sb7Se3 film. The reduction of Sb7Se3 film thickness makes the interface effect stronger than the stress effect, thus hindering the crystallization and causing T C2 It increases with the decrease of Sb7Se3 thickness. In addition, the resistance difference between the high resistance state and the intermediate state, and between the intermediate state and the low resistance state is 1-2 orders of magnitude, which is enough to meet the technical index requirements of phase change information storage, and can also be applied to neuromorphic computing in the context of the artificial intelligence era.

[0057] Comparative Example 1

[0058] Preparation of single-layer Ge2Sb2Te5 thin film with a total thickness of 100 nm

[0059] (1) Slicing

[0060] A diamond knife is used to cut a single crystal P-type (100) oriented silicon wafer with a diameter of 100 mm and a thickness of 0.5 mm into Square pieces are prepared to facilitate physical vapor deposition, high temperature annealing, phase change performance testing and microstructural characterization of single-layer Ge2Sb2Te5 films.

[0061] (2) Cleaning

[0062] The cut single crystal P-type (100) oriented silicon wafer was placed in an acetone solution for ultrasonic cleaning for 6 minutes, and then rinsed with deionized water; then placed in alcohol for ultrasonic cleaning for 6 minutes, and rinsed with deionized water after the ultrasonic cleaning; then placed in a quartz container filled with H2O2 + ammonia solution and heated until boiling, and then rinsed with deionized water; then placed in H2O2 + HCl solution and boiled, boiled and cleaned for 5 minutes, and rinsed with deionized water; finally, the sample was placed in an oven and dried at 120°C for about 20 minutes to obtain a dried single crystal P-type (100) oriented silicon wafer.

[0063] (3) Vacuuming

[0064] Install the sputtering target and the dried single crystal P-type (100) oriented silicon wafer, install the Ge2Sb2Te5 target, start the mechanical pump to roughly vacuum to 20Pa, and then start the molecular pump to finely vacuum to 2.0×10 -4 Pa.

[0065] (4) Sputtering process

[0066] A. Set the sputtering gas argon flow rate to 30 SCCM, the vacuum chamber sputtering pressure to 2.5 Pa, and the target sputtering power to 30 W;

[0067] B. Adjust the gate valve to make the pressure in the chamber reach 4×10 -1 Pa, turn on the Ge2Sb2Te5 target sputtering power supply and pre-sputter for 60s;

[0068] C. Turn on the sample turntable to rotate the dried single crystal P-type (100) oriented silicon wafer at a speed of 20 rpm to ensure that a high-quality film with uniform thickness and composition is obtained;

[0069] D. Calculate the sputtering time according to the design requirements of the film thickness, prepare a single-layer Ge2Sb2Te5 film with a total thickness of 100nm, rotate the dried single-crystalline P-type (100) oriented silicon wafer to the Ge2Sb2Te5 target position, and prepare a 100nm single-layer Ge2Sb2Te5 film at a sputtering speed of 2.439s / nm. After sputtering, turn off the Ge2Sb2Te5 sputtering power supply.

[0070] Comparative Example 2

[0071] Preparation of single-layer Sb7Se3 thin film with a total thickness of 100 nm

[0072] (1) Slicing

[0073] A diamond knife is used to cut a single crystal P-type (100) oriented silicon wafer with a diameter of 100 mm and a thickness of 0.5 mm into Square pieces are prepared to facilitate physical vapor deposition, high temperature annealing, phase change performance testing and microstructural characterization of single-layer Sb7Se3 films.

[0074] (2) Cleaning

[0075] The cut single crystal P-type (100) oriented silicon wafer was placed in an acetone solution for ultrasonic cleaning for 6 minutes, and then rinsed with deionized water; then placed in alcohol for ultrasonic cleaning for 6 minutes, and rinsed with deionized water after the ultrasonic cleaning; then placed in a quartz container filled with H2O2 + ammonia solution and heated until boiling, and then rinsed with deionized water; then placed in H2O2 + HCl solution and boiled, boiled and cleaned for 5 minutes, and rinsed with deionized water; finally, the sample was placed in an oven and dried at 120°C for about 20 minutes to obtain a dried single crystal P-type (100) oriented silicon wafer.

[0076] (3) Vacuuming

[0077] Install the sputtering target and the dried single crystal P-type (100) oriented silicon wafer, install the Sb7Se3 target, start the mechanical pump to roughly vacuum to 20Pa, and then start the molecular pump to finely vacuum to 2.0×10 -4 Pa.

[0078] (4) Sputtering process

[0079] A. Set the sputtering gas argon flow rate to 30 SCCM, the vacuum chamber sputtering pressure to 2.5 Pa, and the target sputtering power to 30 W;

[0080] B. Adjust the gate valve to make the pressure in the chamber reach 4×10 -1 Pa, turn on the Sb7Se3 target sputtering power supply and pre-sputter for 60s;

[0081] C. Turn on the sample turntable to rotate the dried single crystal P-type (100) oriented silicon wafer at a speed of 20 rpm to ensure that a high-quality film with uniform thickness and composition is obtained;

[0082] D. Calculate the sputtering time according to the design requirements of the film thickness, prepare a single-layer Sb7Se3 film with a total thickness of 100nm, rotate the dried single-crystalline P-type (100) oriented silicon wafer to the Sb7Se3 target position, and prepare a 100nm single-layer Sb7Se3 film at a sputtering speed of 2.218s / nm. After sputtering, turn off the Sb7Se3 sputtering power supply.

[0083] The in-situ resistance of the Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) thin films, 100nm single-layer Ge2Sb2Te5 thin films, and 100nm single-layer Sb7Se3 thin films prepared in Example 1, Comparative Example 1, and Comparative Example 2 at different temperatures was tested. The results are as follows Figure 2 shown.

[0084] Depend on Figure 2 It can be seen that the resistance of the deposited thin film material slowly decreases with the increase of temperature, which reflects the temperature characteristics of the semiconductor film. As the annealing temperature gradually increases, the film resistance shows a jump phenomenon, from the high resistance state resistance value to the low resistance state resistance value. It can be seen that the single-layer Ge2Sb2Te5 (100nm) film and the Sb7Se3 (100nm) film only have one resistance jump, while the nano-laminated structure Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) film of the present invention has a secondary resistance jump. The temperature corresponding to the sudden drop point of the film resistance is defined as the phase transition temperature. It can be seen that the nano-laminated structure Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm) film has two phase transition processes from high resistance state to intermediate state and then to low resistance state at 168.2℃ and 212.9℃ respectively. Its three-state resistance value can be used to realize the three-state storage of "0", "1" and "2", which increases the storage density by 50% and helps to improve the data storage capacity.

[0085] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A nano-laminated structure film with multi-resistance non-volatility, characterized in that: The multi-resistance non-volatile nano-laminated structure film is a Ge2Sb2Te5 / Sb7Se3 film, comprising a stacked Ge2Sb2Te5 film and a Sb7Se3 film; the total thickness of the Ge2Sb2Te5 / Sb7Se3 film is 60nm, and the general structural formula is Ge2Sb2Te5(x nm) / Sb7Se3(60-xnm), wherein x represents the thickness of the Ge2Sb2Te5 film, and 0 <x<60。 2. The nano-laminated structure film with multi-resistance non-volatility according to claim 1, characterized in that: The structure of the nano-laminated structure film with multi-resistance non-volatility is one of Ge2Sb2Te5 (5nm) / Sb7Se3 (55nm), Ge2Sb2Te5 (10nm) / Sb7Se3 (50nm), Ge2Sb2Te5 (15nm) / Sb7Se3 (45nm), Ge2Sb2Te5 (20nm) / Sb7Se3 (40nm), and Ge2Sb2Te5 (35nm) / Sb7Se3 (25nm).

3. A method for preparing a nano-laminated structure film having multi-resistance non-volatility according to claim 1 or 2, characterized in that: The steps include: (1) taking a single crystal P-type 100 oriented silicon wafer, splitting, cleaning, and drying to obtain a dried single crystal P-type 100 oriented silicon wafer; (2) Take the dried single crystal P-type 100-oriented silicon wafer, install Ge2Sb2Te5 and Sb7Se3 targets, and evacuate; (3) Adjust the sputtering gas argon flow rate, vacuum chamber sputtering pressure, target sputtering power, adjust the gate valve to control the pressure in the chamber, start the sputtering power supply of Ge2Sb2Te5 and Sb7Se3 targets, and perform pre-sputtering; (4) Turn on the sample turntable to rotate the dried single crystal P-type 100-oriented silicon wafer at a constant speed, and rotate it to the Ge2Sb2Te5 target position to sputter the Ge2Sb2Te5 film. After the sputtering of the Ge2Sb2Te5 film is completed, rotate it to the Sb7Se3 target position to sputter the Sb7Se3 film, thereby obtaining a nano-laminated structure with multi-resistance non-volatility.

4. The method for preparing a nano-laminated structure film having multi-resistance non-volatility according to claim 3, characterized in that: Step (1) is to divide the single crystal P-type 100 oriented silicon wafer into The cleaning step comprises: a. Place the cut single crystal P-type 100 oriented silicon wafer in an acetone solution for ultrasonic cleaning for 5 to 10 minutes, and then rinse with deionized water; b. Then put it in alcohol for ultrasonic cleaning for 5 to 10 minutes, and rinse with deionized water after the ultrasonic cleaning; c. Then place it in a quartz container filled with H2O2 + ammonia solution and heat until it boils, then rinse with deionized water; d. Put it into H2O2+HCl solution and boil it, boil and clean it for 5 to 10 minutes, and rinse it with deionized water.

5. The method for preparing a nano-laminated structure film having multi-resistance non-volatility according to claim 3, characterized in that: The vacuum degree of the vacuum in step (2) is ≤2.0×10 -4 Pa.

6. The method for preparing a nano-laminated structure film having multi-resistance non-volatility according to claim 3, characterized in that: Step (3) The sputtering gas argon flow rate is 30-50 SCCM; the target sputtering power is 20-30 W; the chamber pressure is adjusted to 2×10 -1 ~4×10 -1 Pa; the pre-sputtering time is 50 to 60 seconds.

7. The method for preparing a nano-laminated structure film having multi-resistance non-volatility according to claim 3, characterized in that: In step (4), the speed of uniform rotation of the dried single crystal P-type 100-oriented silicon wafer is 15 to 35 rpm; the sputtering speed of the Ge2Sb2Te5 target is 2.4 to 2.5 s / nm; and the sputtering speed of the Sb7Se3 target is 2.2 to 2.3 s / nm.

8. An application of the multi-resistance non-volatile nanolaminated structure film as claimed in claim 1 as a phase change memory film in neuromorphic computing or large-capacity data storage.

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