Residual pulse broadening interpolation quantization type column-level ADC and CMOS image sensor

Abstract

The invention relates to a residual error pulse broadening interpolation quantization type column-level ADC and a CMOS image sensor, and the residual error pulse broadening interpolation quantization type column-level ADC comprises a comparator, a residual error extraction circuit, a pulse broadening circuit, a coarse quantization counter, a fine quantization counter and an error correction circuit. The comparator is used for comparing a ramp signal and a pixel signal, and the output end of the comparator is connected with the input end of the residual error extraction circuit and the input end of the coarse quantization counter through a first AND gate; the residual error extraction circuit is used for extracting a time difference between an output falling edge of the first AND gate and a first clock rising edge behind the residual error extraction circuit; an output end of the residual error extraction circuit is connected with an input end of the pulse broadening circuit and an input end of the error correction circuit; and the pulse broadening circuit is used for broadening the output of the residual error extraction circuit, and the output end of the pulse broadening circuit is connected with the input end of the fine quantization counter. The problems that an existing SSADC is low in quantization speed and not high in time precision are solved.

Description

Technical Field

[0001] The present application relates to the field of image sensors, and in particular to a residual pulse stretching interpolation quantization type column-level ADC and a CMOS image sensor. Background Art

[0002] In recent years, CMOS image sensors have developed rapidly. Compared with CCD, CMOS image sensors (CIS) have the advantages of low power consumption, low production cost, high integration, fast reading speed and wide dynamic range. They have significant advantages in imaging. CMOS image sensors have always been a hot research topic for scholars at home and abroad. Among them, the speed of the A / D converter directly determines the overall performance of the image sensor. Therefore, the requirements for the speed and power consumption of ADC (analog-to-digital converter) are getting higher and higher. However, the two are often a pair of contradictory indicators. SSADC (single slope ADC) is the most widely used in CIS due to its column sharing and high consistency. However, there are two problems that limit the improvement of ADC speed and accuracy.

[0003] First, SSADC directly uses the one-to-one correspondence between the counter value and the ramp voltage, and records the counter value when the comparator flips. Therefore, the single quantization cycle of SSADC is 2 n CLK, without changing the circuit structure, to improve the quantization speed of the circuit, the only way is to roughly increase the clock speed, but the clock frequency cannot be increased indefinitely, which will increase the design difficulty of the entire circuit, especially the comparator and counter. Another influencing factor is that the comparator flipping moment is not always aligned with the clock edge. The flipping moment will produce a time margin with the previous clock edge. The quantization loss of this time margin limits the further improvement of the ADC resolution. One of the common solutions is to introduce a higher frequency clock to improve the ADC resolution, but this will have the same impact as the previous problem.

[0004] Although there are some solutions to the above problems, there is no particularly good solution to achieve the goal of picosecond time resolution. Summary of the invention

[0005] The present invention provides a residual pulse stretching interpolation quantization type column-level ADC to solve the problems of slow quantization speed and low time precision of the current SSADC.

[0006] The present invention provides a residual pulse stretching interpolation quantization type column-level ADC, comprising: a comparator, a residual extraction circuit, a pulse stretching circuit, a coarse quantization counter, a fine quantization counter and an error correction circuit;

[0007] The comparator is used to compare the ramp signal and the pixel signal, and the output end of the comparator is connected to the input end of the residual extraction circuit and the input end of the coarse quantization counter through a first AND gate;

[0008] The residual extraction circuit is used to extract the time difference between the output falling edge of the first AND gate and the first clock rising edge after itself, and the output end of the residual extraction circuit is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit;

[0009] The pulse stretching circuit is used to stretch the output of the residual extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter;

[0010] The carry output terminal and the sign output terminal of the fine quantization counter are both connected to the input terminal of the error correction circuit;

[0011] The output end of the error correction circuit is connected to the input end of the coarse quantization counter, and the error correction circuit is used to generate an error correction signal according to the carry output and the sign output of the fine quantization counter and the output of the residual extraction circuit.

[0012] Compared with the related art, the present invention divides the quantization process into coarse quantization and fine quantization by interpolation, which can improve the quantization speed. For example, in the case of 7-bit coarse quantization and 4-bit fine quantization, the present invention can improve the quantization speed by 2 11 The quantization cycle is shortened to 2 7 +2 4 quantization cycle (there is 1 redundant correction bit in fine quantization), reducing by 93%. At the same time, due to its pulse broadening characteristics, this circuit can improve the circuit's tolerance to high-speed quantization. At the same time, the design of the two-step ADC can ensure that the fine quantization counter only needs to work for 16 clock cycles, reducing power consumption and solving the current SSADC's slow quantization speed and low time accuracy problems.

[0013] Compared with the related art, the present invention unifies part of the pulse stretching operations after the coarse quantization is completed, thereby realizing the column sharing of the first capacitor of the pulse stretching circuit and effectively saving the circuit area.

[0014] Compared with the related art, the present invention proposes an RC integral pulse stretching circuit, and this structure enables the ADC to have a higher time resolution.

[0015] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit architecture of a residual pulse stretching interpolation quantization type column-level ADC in one embodiment of the present invention;

[0017] Figure 2 is a circuit diagram of a comparator in one embodiment of the present invention;

[0018] Figure 3 is a circuit diagram of a residual error extraction circuit in one embodiment of the present invention;

[0019] Figure 4 is a signal timing diagram of a residual error extraction circuit in one embodiment of the present invention;

[0020] Figure 5 is a circuit diagram of a pulse stretching circuit in one embodiment of the present invention;

[0021] Figure 6 is an integral schematic diagram of a pulse stretching circuit in one embodiment of the present invention;

[0022] Figure 7 is a signal timing diagram of a pulse stretching circuit in one embodiment of the present invention;

[0023] Figure 8 1 is a schematic diagram of the resistance equivalent of a pulse stretching circuit in one embodiment of the present invention;

[0024] Fig. 9 is a schematic diagram of the splicing of a coarse quantization counting result and a fine quantization counting structure in one embodiment of the present invention;

[0025] Fig.10 is a circuit diagram of a fine quantization counter in one embodiment of the present invention;

[0026] Fig.11 is a circuit diagram of a coarse quantization counter in one embodiment of the present invention;

[0027] Fig.12 is a schematic diagram of carry and misalignment in one embodiment of the present invention;

[0028] Fig.13 is a timing diagram of a counter rollover error in one embodiment of the present invention;

[0029] Fig.14 is a circuit diagram of a signal generating circuit in one embodiment of the present invention;

[0030] Fig.15 is a circuit diagram of a pulse selection circuit in one embodiment of the present invention;

[0031] Fig.16 is a timing diagram of error correction in one embodiment of the present invention;

[0032] Fig.17It is a working timing diagram of the residual pulse stretching interpolation quantization type column-level ADC in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0034] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0035] In an embodiment of the present invention, a residual pulse stretching interpolation quantization type column-level ADC is provided.

[0036] like Figure 1 As shown, in this embodiment, the ADC includes: a comparator, a residual extraction circuit (Tresidue), a pulse stretching circuit (TA), a coarse quantization counter, a fine quantization counter and an error correction circuit.

[0037] The comparator is used to compare the ramp signal V ramp and pixel signal V pixleThe output of the comparator is connected to the input of the residual extraction circuit and the input of the coarse quantization counter through the first AND gate. The two inputs of the first AND gate are respectively used to access the output of the comparator and the comparator enable signal Como en. When the output of the comparator is flipped, the output signal Φcomp of the first AND gate will also be flipped. The comparator enable signal Como en can select the flip signal of the control comparator, shield the invalid flip interval, and generate the output signal Φcomp of the first AND gate.

[0038] In this embodiment, the comparator uses an input offset storage circuit to store the offset voltage. Figure 2 Specifically, the comparator is a continuous time comparator, which includes a cascaded first operational amplifier OPA1 and a second operational amplifier OPA2; the in-phase input terminal and the reverse input terminal of the first operational amplifier OPA1 are respectively used to access the ramp signal V ramp and pixel signal V pixle , the non-inverting output terminal of the second operational amplifier OPA2 is the output terminal of the continuous-time comparator; the non-inverting input terminal and the reverse output terminal of the first operational amplifier OPA1, as well as the reverse input terminal and the non-inverting output terminal are connected through the first control switch S1, and the non-inverting input terminal and the reverse output terminal of the second operational amplifier OPA2, as well as the reverse input terminal and the non-inverting output terminal are connected through the second control switch S2; the current sources of the first operational amplifier OPA1 and the second operational amplifier OPA2 both adopt a cascode structure.

[0039] In the initial state of the comparator, the first control switch S1 and the second control switch S2 are turned on at the same time. After sampling the input signal (ramp signal and pixel signal), the first control switch S1 and the second control switch S2 are turned off in sequence to reduce the impact of charge injection. The first operational amplifier OPA1 and the second operational amplifier OPA2 have the same structure. The two-stage cascade forms a continuous time hysteresis structure, which can effectively improve the gain. The use of a continuous time comparator is determined by the principle of this circuit. This is because the flip point of the dynamic comparator is discrete, and the extracted time margin is basically a fixed value, which is not applicable to the interpolation principle of the present invention. The current source of the two operational amplifiers uses a cascode structure to improve the current replication accuracy. The ramp signal V ramp With the pixel signal V pixle The range is in the "sweet spot" of the comparator. This is done to make the flip delay of the comparator at different reversal points as consistent as possible, thereby reducing the impact on INL (integral nonlinearity error).

[0040] The internal structure of the comparator in this embodiment is as follows Figure 3As shown, the current source adopts a cascode structure (a first transistor M1 and a second transistor M2), the drain end of the first transistor M1 is connected to the source end of the second transistor M2, the lower transistor is a diode connection, and the gate of the other transistor is connected to the drain of the opposite transistor, forming a positive feedback structure. It should be noted that the internal structure of the comparator is a mature circuit structure. The present invention focuses on the selection of the current source structure, and the other parts of the structure are not specifically described. Please refer to Figure 3 Compared with other types of comparators, this comparator structure can obtain a shorter and more consistent time delay in the quantization interval while obtaining a larger gain.

[0041] The residual extraction circuit is used to extract the time difference between the output falling edge of the first AND gate (the falling edge of Φcomp) and the first clock rising edge (the falling edge and rising edge of the clock signal CLK) after itself (referring to the output falling edge of the first AND gate) (the pulse width of the output signal Tr of the residual extraction circuit represents the time difference), and the output end of the residual extraction circuit (output signal Tr) is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit.

[0042] In this embodiment, refer to Figure 3 The residual extraction circuit includes a first D flip-flop and a NOR gate; the D end of the first D flip-flop is connected to the output end of the first AND gate (for accessing the output signal Φcomp of the first AND gate), the CK end of the first D flip-flop is used to access the clock signal CLK, the QB end of the first D flip-flop is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the first AND gate (for accessing the output signal Φcomp of the first AND gate), and the output end of the NOR gate is the output end of the residual extraction circuit after passing through the buffer.

[0043] In this embodiment, the input end of the residual error extraction circuit is composed of a D flip-flop and a NOR gate in series. The waveforms of the output signal Tr and related signals of the residual error extraction circuit are as follows: Figure 4 , where TA_en is the TA enable signal, which is used to control the pulse stretching operation when fine quantization starts after coarse quantization ends.

[0044] The pulse stretching circuit is used for stretching the output of the residual extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter.

[0045] In this embodiment, the coarse quantization counter is used to implement 7-bit counting, the fine quantization counter is used to implement 4-bit counting, and the pulse stretching circuit is used to implement 16-fold pulse stretching.

[0046] Reference Figure 6Specifically, the pulse stretching circuit includes a first RC integration circuit, a second RC integration circuit and a third operational amplifier OPA3 connected in parallel; the first RC integration circuit includes a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is connected to the first end of the first capacitor C1 through a first series switch (the control signal is the output signal Tr of the residual extraction circuit), and the control end of the first series switch is connected to the output end of the residual extraction circuit; the second RC integration circuit includes a second resistor R2 and a second capacitor C2, the first end of the second resistor R2 is connected to the first end of the second capacitor C2 through a second series switch (the control signal is a TA enable signal), and the control end of the second series switch is used to access the TA enable signal; the second ends of the first resistor R1 and the second resistor R2 are both connected to the positive power supply VDD, and the first capacitor C1 and the second end of the second capacitor C2 are both connected to the negative power supply VSS; the first end and the second end of the first capacitor C1 are also connected through the first return to zero switch, the first end and the second end of the second capacitor C2 are also connected through the second return to zero switch, the in-phase input terminal and the reverse output terminal of the third operational amplifier OPA3 and the reverse input terminal and the in-phase output terminal are all connected through the third return to zero switch, and the control ends of the first return to zero switch, the second return to zero switch and the third return to zero switch are all used to access the return to zero signal Φaz; the first end of the first capacitor C1 is connected to the in-phase input terminal of the third operational amplifier OPA3, the first end of the second capacitor C2 is connected to the reverse input terminal of the third operational amplifier OPA3, and the in-phase output terminal of the third operational amplifier OPA3 is the output terminal of the pulse stretching circuit; the size ratio of the first capacitor and the second capacitor is 16 / 1.

[0047] The structure of the pulse stretching circuit in the present invention is as follows: Figure 5 On the left are two RC integrators, including the top resistor, two integrating capacitors connected to the current source, and four switches. The capacitors are 16C and 1C. On the right is a static comparator that uses the same Figure 2 The comparator has the same structure as in .

[0048] The working process is as follows: Figure 6 , Figure 7 and Figure 8 , first, the comparator and the integral capacitor are automatically reset to zero and reset when Φaz is at a high level. After the output signal Tr of the residual extraction circuit (the pulse duration in the signal is Tr), the 1C capacitor on the right (the second capacitor) is charged by RC, and after a time Tr, the voltage reaches V1, and this voltage is stored. After the coarse quantization cycle of all columns is over. TA_en is set high, and the fine quantization counter is started at the same time, and the 16C capacitor on the left is charged. Since the size of the two capacitors is 16:1, the time constant τ is 16:1. Therefore, when the two reach the same voltage, the 16C capacitor (the first capacitor) needs time 16Tr. The derivation process is as follows:

[0049]

[0050] The two capacitors are directly connected to the hysteresis comparator. After the output voltage Vn and Vp cross at the voltage V1, the comparator is controlled to flip, and the fine quantization counter latch signal φstretch (the output signal of the pulse stretching circuit) flips. The delay of the comparator itself is Δt, which will be eliminated as a fixed error in the double sampling operation.

[0051] Since the 16C capacitor is quite large (about 4 pF), it is shared by the columns. The 16 columns of readout circuits share the 16C capacitor, so each column only needs to introduce a capacitor of about 0.25 pF, which significantly saves area consumption.

[0052] In addition, the traditional constant current source integral type TA cannot realize fast charging of the integral capacitor in a short time. When the integral capacitor is a certain value, a larger current source is needed for higher frequency application scenarios. In order to reduce the influence of the switch resistance voltage divider on the integral voltage, the switch size needs to be larger. However, when the current source is started, the charge injection and clock feedthrough from the switch will also affect the initial value of the integral voltage, which limits the use of TA for higher frequency circuits. For the corresponding RC type TA (the pulse stretching circuit used in the present invention), the switch resistance Rs itself can be used as part of the integral resistance R (the resistance of R1 and R2), so there is no need to use a larger switch size. In this design, an nmos switch is used with an integral range of 0-1.2V. Obviously, when the switch resistance works in this range, there will be a resistance change ΔRs, such as Figure 8 , considering its influence on the integral curve, the following derivation is made:

[0053] Assuming that the final value of the integral voltage V1 is a minimum value v1, then in the minimum voltage interval (0, v1), it can be approximately considered that Rs increases by ΔRs1. According to the above formula, the 1C capacitor and the 16C capacitor use Δt1 and 16*Δt1 respectively to reach v1. Similarly, in the minimum interval (v1, v2), the two use Δt2 and 16*Δt2 to integrate from voltage v1 to voltage v2. Therefore, in any sub-interval from 0 to V1 (v i ,v i+1), the two-point integration time is Δti and 16*Δti respectively, then for any integral final value V1, the integration time of the 16C capacitor is 16 times that of the 1C integration capacitor. In other words, although the switch resistance change ΔRs will cause the charging curve to be a pseudo-RC curve, since the relative size of the resistance of the two branches has not changed, the relative charging time of the two branches will only be related to the charging capacitance, which is obviously what the present invention expects. Therefore, when designing the switch size, only two switches of the same size need to be used, and the parasitic capacitance of the switch only needs to be much smaller than the charging capacitance C. The channel length is the minimum process size, and the channel width is 3 to 5 times the minimum process size.

[0054] The carry output terminal (output signal Co) and the sign output terminal (output signal Sign) of the fine quantization counter are both connected to the input terminal of the error correction circuit; the output terminal (output signal pulse) of the error correction circuit is connected to the input terminal of the coarse quantization counter, and the error correction circuit is used to generate an error correction signal based on the carry output signal Co and the sign output signal Sign of the fine quantization counter and the output signal Tr of the residual extraction circuit.

[0055] Reference Fig.10 and Fig.11 In this embodiment, the fine quantization counter includes a second AND gate and six groups of trigger components connected in series, and the coarse quantization counter includes a latch connected in series, a first two-to-one MUX and seven groups of trigger components.

[0056] Each group of trigger components includes a second D trigger and a second two-to-one MUX, and the Q and QB ends of the second D trigger are connected to the D end through the second two-to-one MUX (the selection signal is LOCK); the Q and QB ends of the previous second D trigger are also connected to the CK end of the next second D trigger through the third two-to-one MUX (the selection signal in the fine quantization counter is UD LSB, and the selection signal in the coarse quantization counter is UD MSB).

[0057] The output end of the pulse stretching circuit is connected to the CK end of the first second D flip-flop in the fine quantization counter through the second AND gate. The other input end of the second AND gate is used to access the clock signal CLK. In the fine quantization counter, the Q end of each second D flip-flop is respectively four counting output ends, a carry output end and a sign output end (used to output signals CNT0, CNT1, CNT2, CNT3, Co and Sign, respectively).

[0058] In the coarse quantization counter, the G end of the latch is connected to the output end of the first AND gate, the D end of the latch is used to access the clock signal CLK, the Q end of the latch (used to output the signal DDR) and the output end of the error correction circuit are connected to the CK end of the first second D flip-flop through the first two-to-one MUX (the selection signal is Calib), and the Q ends of each second D flip-flop are 7 counting output ends in turn (used to output signals CNT4, CNT5, CNT6, CNT7, CNT8, CNT9, and CNT10, respectively).

[0059] In summary, if Fig.10 The fine quantization counter is composed of 6 D flip-flops connected in series asynchronously. Two two-to-one MUXs are connected in series between each D flip-flop. The output is connected to the clock input of the next D flip-flop and the D end of the current D flip-flop, respectively, to select the counting direction (addition and subtraction, controlled by the signal UD) and lock the current data (must be locked before switching the counting direction, otherwise the previous count value will change after the flip, controlled by the signal LOCK). The size of the count value is determined by the number of rising edges of the clock at the clock input of the first D flip-flop. The AND input of the left side of the fine quantization counter is connected to CLK and φcomp. When φcomp is high, the number of rising edges of the input clock is selected. In the fine quantization stage, ideally, the counter count value will only be 00001111, but in reality, the static comparator will have a hysteresis after the voltage intersection. In addition, due to process errors and comparator delays, pulse broadening, Tr cannot be accurately stretched by 16 times. It may also be 16.5 or 17 times. If only a four-bit counter is used, an overflow may occur. For example, after 1111, the counter will return to 0000, which is obviously undesirable in the present invention. Therefore, an overflow bit is introduced, and the last D flip-flop is used as a sign bit (Sign), because the count value may be less than 0 during the double sampling process. For example, the first upward count is from 000000→000010, and the second downward count is from 000010→111110 (+2→+10→-31→-30).

[0060] like Fig.11 As shown, the coarse quantization counter is composed of 7 D flip-flops connected asynchronously in series, with a latch connected at the front end, one of the input ends of which is the counter clock. The output signal φcomp from the comparator is used as the latch control signal of the front latch to control the number of rising edges of the input clock, thereby controlling the number of flips of the D flip-flops connected in series at the rear. In addition, the present invention adds an error correction unit in front of the coarse quantization counter, such as Fig.11This error correction unit selects the clock signal and the correction pulse signal (output signal pulse of the error correction circuit) at the input end through a two-choice MUX. When the control signal Calib=0, the circuit works in the normal counting mode, Calib=1, and the pulse is connected to the first D flip-flop input. By inputting a rising edge in the add or subtract state of the counter, the coarse quantization counter can be added or subtracted by 1, thereby realizing the correction of the error value. After the correction is completed, Calib is reset to 0 to prepare for the next quantization. In addition, if you need to implement the operation of adding 2, you only need to input two rising edge pulses.

[0061] In addition, the counting directions of the coarse quantization counter and the fine quantization counter are opposite, because the time residual extraction circuit extracts the time between the falling edge of Φcomp and the rising edge of the next clock (Tr, Tresidue), and the time margin we actually need is the time between the falling edge of Φcomp and the rising edge of the previous clock (Treal_residue). There is such a relationship between the two:

[0062] Tresidue+Treal_residue=1CLK

[0063] Therefore, the final coarse quantization count value and fine quantization count value cannot be directly spliced ​​together, and a difference operation needs to be performed on the two. This process is achieved by inverting the counting direction control bit (UD) of the fine quantization counter. In addition, this process will cause borrow and carry, which can be achieved by correcting the coarse quantization counter through Co and Sign. Fig. 9 The schematic diagram of adding the coarse quantization result and the fine quantization result is given, wherein CNT0, CNT1, CNT2, and CNT3 are used as the first four bits, and CNT4, CNT5, CNT6, CNT7, CNT8, CNT9, and CNT10 are used as the last seven bits, and Co and Sign are added to CNT4 and CNT5 respectively, and DDR is added to CNT3. Fig.12 The specific situations of carry and borrow in the fine quantization process are given, where the falling edge of φcomp1 and φcomp2 and the first rising edge of the clock signal CLK after themselves are the coarse quantization residuals of the quantization reset signal and the exposure signal respectively. Table 1 gives the situations of carry and borrow in the fine quantization counter.

[0064] Table 1 shows the carry and borrow of the fine quantization counter

[0065] Sign Co Carry / Borrow 0 0 0 0 1 Carry 1MSB 1 0 Borrow 2MSB 1 1 Borrow 1MSB

[0066] In some embodiments, the error correction circuit includes: a signal generating circuit (used to generate a signal Flag, refer to Fig.14 ) and pulse selection circuit (refer to Fig.15 ). The signal generating circuit includes a third AND gate, a fourth AND gate, a third D flip-flop and a fourth D flip-flop, the two input ends of the third AND gate are respectively connected to the output end of the residual extraction circuit (access signal Tr) and the clock signal CLK, the output end of the third AND gate is connected to the CK end of the third D flip-flop, the D end and QB end of the third D flip-flop are both connected to the CK end of the fourth D flip-flop, the two output ends of the fourth AND gate are respectively connected to the Q end of the fourth D flip-flop and the QB end of the latch (access signal DDRB), the output end of the fourth AND gate is the output end of the signal generating circuit, and the D end of the fourth D flip-flop is connected to the 1.2V positive power supply VCC12; the pulse selecting circuit includes a fifth AND gate, a sixth AND gate, The seventh AND gate and the XOR gate, the two input ends of the XOR gate are respectively connected to the carry output end and the sign output end of the fine quantization counter (respectively connected to the signals Co and Sign), the two input ends of the fifth AND gate are respectively connected to the output end of the signal generation circuit and the first pulse signal pulse1, the two input ends of the sixth AND gate are respectively connected to the output end of the XOR gate and the second pulse signal pulse2, the two input ends of the seventh AND gate are respectively connected to the sign output end of the fine quantization counter and the third pulse signal pulse3, the output ends of the fifth AND gate, the sixth AND gate and the seventh AND gate together constitute the output end of the error correction circuit, and the pulse selection circuit will select one of the three pulse signals for output. Among them, the three pulse signals need to be input during Calib=1, the first pulse signal pulse1 needs to be input before the rising edge of sub_en, and the second pulse signal pulse2 and the third pulse signal pulse3 are input at sub_en=1. They are column-shared signals, which are uniformly input by external digital circuits.

[0067] Specifically, there is a flip error in the quantization process that needs to be corrected, such as Fig.13 When the falling edge of Φcomp is very close to the next rising edge of the clock, the residual extraction circuit may identify Φcomp as after the current clock rising edge and extract a time residual close to one clock cycle, but the coarse quantization counter will identify Φcomp as before the current clock rising edge. Therefore, it can be considered that the counter is flipped one less time, and a Flag flag needs to be generated for an error correction with 1MSB added. Fig.13 , Figure 4 The timing diagram of error generation and the decision circuit (signal generating circuit) of the Flag bit are given respectively.

[0068] When it happens Fig.13 When the flip error in Fig.14The time margin Tr and CLK will generate two high-level pulse signals after passing through an AND gate. A D flip-flop connected as a counter will record the number of rising edges. After flipping twice, the output of the second flip-flop will be set high. If and only if the two input ends of the last AND gate are high at the same time after an erroneous flip, the Flag is set to 1.

[0069] After obtaining the flag, error correction will be performed after quantization. Since digital double sampling is required, flip errors may occur in both quantization processes, so correction is required immediately after each quantization. After the double sampling process is completed, carry and borrow correction are performed uniformly. The two error correction processes are performed by inputting a high-level pulse pulse at the MSB input. If two MSBs need to be corrected, two pulses need to be input. Addition and subtraction are controlled by the sign signal Sign. The structure of the entire correction circuit is as follows: Fig.15 , Fig.16 . By selecting pulse1, pulse2, and pulse3 and inputting the MSB counter input terminal through the flag bit, the quantization result can be corrected. Fig.15 , the signal UDMSB is generated according to the signals Sign, suben and UD through the NAND gate and the AND gate.

[0070] In summary, the present invention provides a residual pulse stretching interpolation quantization type column-level ADC. In one embodiment, the signal changes during its operation are as follows: Fig.17 As shown. After automatic zeroing (φaz), coarse quantization begins, the coarse quantization counter starts, the ramp generator voltage starts to decrease, the ramp signal is compared with the pixel signal in the comparator, and the comparator flip signal Φcomp is generated to control the coarse quantization counter to stop. After the coarse quantization process is completed, the residual extraction circuit (Tr) is used to extract the time margin between the comparator flip signal Φcomp and the next clock rising edge, and the time margin is converted into the corresponding voltage storage. After the coarse quantization of all columns is completed, TA will widen the time margin (Tresidue) and then use the clock for quantization. The quantized code value is the value of the fine quantization counter. After the fine quantization is completed, the digital correction circuit (EC) will correct the final result through the flag bit generated during the counting process to obtain the quantization result.

[0071] It can be seen from the above embodiments that the residual pulse stretching interpolation quantization column-level ADC provided by the present invention has the following technical effects:

[0072] In the case of 7-bit coarse quantization and 4-bit fine quantization, the present invention can 11 The quantization cycle is shortened to 2 7 +2 4quantization cycle (there is 1 redundant correction bit in fine quantization), reducing by 93%. At the same time, due to its pulse broadening characteristics, this circuit can improve the circuit's tolerance to high-speed quantization. At the same time, the design of the two-step ADC can ensure that the fine quantization counter only needs to work for 16 clock cycles, reducing power consumption and solving the current SSADC's slow quantization speed and low time accuracy problems.

[0073] The present invention further provides a CMOS image sensor, comprising the residual pulse stretching interpolation quantization type column-level ADC provided in the present invention.

[0074] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0075] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A residual pulse stretching interpolation quantization type column-level ADC, characterized in that: include: Comparator, residual extraction circuit, pulse stretching circuit, coarse quantization counter, fine quantization counter and error correction circuit; The comparator is used to compare the ramp signal and the pixel signal, and the output end of the comparator is connected to the input end of the residual extraction circuit and the input end of the coarse quantization counter through a first AND gate; The residual extraction circuit is used to extract the time difference between the output falling edge of the first AND gate and the first clock rising edge after itself, and the output end of the residual extraction circuit is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit; The pulse stretching circuit is used to stretch the output of the residual extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter; The carry output terminal and the sign output terminal of the fine quantization counter are both connected to the input terminal of the error correction circuit; The output end of the error correction circuit is connected to the input end of the coarse quantization counter, and the error correction circuit is used to generate an error correction signal according to the carry output and the sign output of the fine quantization counter and the output of the residual extraction circuit.

2. The residual pulse stretching interpolation quantization column-level ADC according to claim 1, characterized in that: The comparator is a continuous time comparator, and the continuous time comparator includes a first operational amplifier and a second operational amplifier connected in cascade; The in-phase input terminal and the inverting input terminal of the first operational amplifier are used to receive the ramp signal and the pixel signal respectively, and the in-phase output terminal of the second operational amplifier is the output terminal of the continuous-time comparator; The in-phase input terminal and the inverting output terminal of the first operational amplifier are connected via a first control switch, as are the inverting input terminal and the in-phase output terminal. The in-phase input terminal and the inverting output terminal of the second operational amplifier are connected via a second control switch.

3. The residual pulse stretching interpolation quantization type column-level ADC according to claim 2, characterized in that: The current sources of the first operational amplifier and the second operational amplifier both adopt a cascode structure.

4. The residual pulse stretching interpolation quantization type column-level ADC according to claim 1, characterized in that: The residual extraction circuit includes a first D flip-flop and a NOR gate; The D end of the first D flip-flop is connected to the output end of the first AND gate, the CK end of the first D flip-flop is used to access the clock signal, the QB end of the first D flip-flop is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the first AND gate, and the output end of the NOR gate is the output end of the residual extraction circuit after passing through a buffer.

5. The residual pulse stretching interpolation quantization type column-level ADC according to claim 1, characterized in that: The coarse quantization counter and the fine quantization counter have opposite counting directions.

6. The residual pulse stretching interpolation quantization type column-level ADC according to claim 5, characterized in that: The coarse quantization counter is used to realize 7-bit counting, the fine quantization counter is used to realize 4-bit counting, and the pulse stretching circuit is used to realize 16-fold pulse stretching.

7. The residual pulse stretching interpolation quantization type column-level ADC according to claim 6, characterized in that: The pulse stretching circuit includes a first RC integration circuit, a second RC integration circuit and a third operational amplifier connected in parallel; The first RC integration circuit includes a first resistor and a first capacitor, the first end of the first resistor is connected to the first end of the first capacitor through a first series switch, and the control end of the first series switch is connected to the output end of the residual extraction circuit; The second RC integration circuit includes a second resistor and a second capacitor, a first end of the second resistor is connected to a first end of the second capacitor through a second series switch, and a control end of the second series switch is used to access a TA enable signal; The second ends of the first resistor and the second resistor are both connected to a positive power supply, and the second ends of the first capacitor and the second capacitor are both connected to a negative power supply; The first end and the second end of the first capacitor are also connected through a first return-to-zero switch, the first end and the second end of the second capacitor are also connected through a second return-to-zero switch, the in-phase input end and the inverting output end of the third operational amplifier are connected as well as the inverting input end and the in-phase output end thereof are connected through a third return-to-zero switch, and the control ends of the first return-to-zero switch, the second return-to-zero switch and the third return-to-zero switch are all used to receive a return-to-zero signal; The first end of the first capacitor is connected to the non-inverting input end of the third operational amplifier, the first end of the second capacitor is connected to the inverting input end of the third operational amplifier, and the non-inverting output end of the third operational amplifier is the output end of the pulse stretching circuit; The size ratio of the first capacitor to the second capacitor is 16 / 1.

8. The residual pulse stretching interpolation quantization type column-level ADC according to claim 6, characterized in that: The fine quantization counter includes a second AND gate and six groups of flip-flop components connected in series, and the coarse quantization counter includes a latch connected in series, a first two-to-one MUX and seven groups of flip-flop components; Each group of the trigger components includes a second D trigger and a second two-to-one MUX, and the Q terminal and QB terminal of the second D trigger are connected to the D terminal through the second two-to-one MUX; The Q end and the QB end of the previous second D flip-flop are also connected to the CK end of the next second D flip-flop through a third two-to-one MUX; The output end of the pulse stretching circuit is connected to the CK end of the first second D flip-flop in the fine quantization counter through the second AND gate. In the fine quantization counter, the Q end of each second D flip-flop is respectively four counting output ends, the carry output end and the sign output end; In the coarse quantization counter, the G end of the latch is connected to the output end of the first AND gate, the D end of the latch is used to access the clock signal, the Q end of the latch and the output end of the error correction circuit are connected to the CK end of the first second D flip-flop through the first two-to-one MUX, and the Q ends of each second D flip-flop are 7 counting output ends respectively.

9. The residual pulse stretching interpolation quantization type column-level ADC according to claim 1, characterized in that: The error correction circuit comprises: a signal generation circuit and a pulse selection circuit; The signal generating circuit comprises a third AND gate, a fourth AND gate, a third D flip-flop and a fourth D flip-flop, two input ends of the third AND gate are respectively connected to the output end of the residual extraction circuit and the clock signal, the output end of the third AND gate is connected to the CK end of the third D flip-flop, the D end and the QB end of the third D flip-flop are both connected to the CK end of the fourth D flip-flop, two output ends of the fourth AND gate are respectively connected to the Q end of the fourth D flip-flop and the QB end of the latch, and the output end of the fourth AND gate is the output end of the signal generating circuit; The pulse selection circuit includes a fifth AND gate, a sixth AND gate, a seventh AND gate and an XOR gate, the two input ends of the XOR gate are respectively connected to the carry output end and the sign output end of the fine quantization counter, the two input ends of the fifth AND gate are respectively connected to the output end of the signal generating circuit and the first pulse signal pulse1, the two input ends of the sixth AND gate are respectively connected to the output end of the XOR gate and the second pulse signal pulse2, the two input ends of the seventh AND gate are respectively connected to the sign output end of the fine quantization counter and the third pulse signal pulse3, and the output ends of the fifth AND gate, the sixth AND gate and the seventh AND gate together constitute the output end of the error correction circuit.

10. A CMOS image sensor, characterized in that: include: The residual pulse stretching interpolation quantization type column-level ADC according to any one of claims 1 to 9.

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