Safety state detection device, method and equipment for vehicle-mounted speed sensor

Abstract

The invention relates to a safety state detection device, method and equipment for a vehicle-mounted speed sensor.The device comprises a speed sensor, the device comprises a sensor interface module, a speed sensor interface signal processing module and an FPGA processing module which are connected in sequence, and the speed sensor outputs two paths of speed sensor pulse signals; the signal is transmitted to the two parallel speed sensor interface signal processing modules through the sensor interface module; the speed sensor interface signal processing module carries out signal acquisition and signal state detection on an input speed sensor pulse signal, and simultaneously sends acquisition and state detection results to two sub-modules of the FPGA processing module. And the two sub-modules of the FPGA processing module respectively process the received acquisition and state detection results, compare the processing results and output a safety state judgment result of the speed sensor. Compared with the prior art, the speed sensor has the advantages of realizing safety state detection, fault prompt and the like of the speed sensor.

Description

Technical Field

[0001] The present invention relates to the technical field of rail transit signal detection, and in particular to a safety state detection device, method and equipment for a vehicle-mounted speed sensor. Background Art

[0002] In the rail transit signal industry, the speed sensor, as an external device, provides safe and reliable speed information to the entire vehicle system in real time, so it is necessary to monitor the operating status of this key external sensor in real time. Existing speed sensor equipment itself cannot provide safety status information. When the speed sensor signal fails abnormally, which affects the safe operation of the train, the system cannot effectively detect it. Especially when the system is in a zero-speed state, the monitoring personnel cannot determine the reason for the zero-speed state, whether it is due to a speed sensor device connection failure or the speed sensor is in a stopped state, which is very easy to cause misjudgment.

[0003] How to achieve safe status detection of vehicle-mounted speed sensors has become a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present invention is to provide a safety state detection device and method for a vehicle-mounted speed sensor in order to overcome the defects of the prior art.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] According to one aspect of the present invention, a safety state detection device for a vehicle-mounted speed sensor is provided, the device is used for state detection of the speed sensor, the device comprises a sensor interface module, two identical speed sensor interface signal processing modules and an FPGA processing module connected in sequence, the FPGA processing module comprises a parallel FPGA_A processing submodule and a FPGA_B processing submodule;

[0007] The speed sensor outputs two speed sensor pulse signals, which are respectively transmitted to two parallel speed sensor interface signal processing modules through the sensor interface module;

[0008] Each speed sensor interface signal processing module performs signal acquisition and signal status detection on the input speed sensor pulse signal, and sends the acquisition result and status detection result to the two processing sub-modules of the FPGA processing module at the same time;

[0009] The two processing submodules of the FPGA processing module of each channel compare the collection result and the state detection result received from the channel, and output the safety state judgment result of the speed sensor;

[0010] The two processing submodules of each FPGA processing module compare the collection results received from the other channel with each other, and output the safety status judgment result of the speed sensor.

[0011] Preferably, the speed sensor interface signal processing module includes a signal acquisition processing module;

[0012] The signal acquisition and processing module is used to collect the speed sensor pulse signal of at least one speed sensor, and the received speed sensor pulse signal is first subjected to RC filtering processing by the front-stage signal processing circuit, and the processed signal is sent to the comparison circuit, and compared with the reference circuit inside the comparison circuit. The compared signal is then isolated by the first isolation circuit, and two pulse signals with the same phase and frequency as the speed sensor pulse signal are output, which are OUT1_A signal and OUT1_B signal respectively.

[0013] More preferably, the speed sensor interface signal processing module further comprises a signal state detection module in parallel with the signal acquisition processing module;

[0014] The signal state detection module is used to detect the signal state of the speed sensor pulse signal of the speed sensor. The received speed sensor pulse signal is first converted into a level by a level conversion circuit, and the processed signal is sent to the in-phase comparator and the inverting comparator for processing at the same time; the in-phase comparator and the inverting comparator respectively output pulse signals OUT3_A and OUT3_B signals with an anti-phase and the same frequency as the speed sensor pulse signal, and pulse signals OUT2_A and OUT2_B signals with the same phase and frequency as the speed sensor pulse signal.

[0015] More preferably, the input signal of the in-phase comparator enters from the non-inverting input terminal of the comparator, and is compared with the reference voltage VREF2 of the in-phase comparator. The compared signal is then isolated by the third isolation circuit, thereby outputting pulse signals OUT3_A and OUT3_B with the same frequency and opposite phase to the speed sensor pulse signal;

[0016] The input signal of the inverting comparator enters from the negative input terminal of the comparator and is compared with the reference voltage VREF1 of the inverting comparator. The compared signal is then isolated by the second isolation circuit to output pulse signals OUT2_A and OUT2_B with the same phase and frequency as the speed sensor pulse signal.

[0017] More preferably, the negative phase reference voltage VREF1 is set to 0.8VCC, where VCC is the power supply voltage.

[0018] Preferably, the structures of the FPGA_A processing submodule and the FPGA_B processing submodule are the same;

[0019] The FPGA_A processing submodule and the FPGA_B processing submodule both include a self-check unit, a cache unit, and a parallel processing unit and a detection unit; one end of the parallel processing unit and the detection unit is connected to the self-check unit, and the other end is connected to the cache unit.

[0020] More preferably, in the initial power-on stage of the safety state detection device, the self-checking unit generates a self-checking excitation signal according to a command transmitted from the outside, and then sends it to the processing unit for processing;

[0021] The processing unit processes the received self-test excitation signal or the output signal of the signal acquisition processing module, wherein the processing includes pulse value counting, phase difference counting, high level and cycle counting, and then transmits these count values ​​to the cache unit.

[0022] More preferably, the detection unit determines the level relationship between the output signals of the received signal state detection module, determines the safety state of the speed sensor according to the determination result, and sends the determination result to the cache unit;

[0023] The cache unit aggregates and caches the information sent by the processing unit and the detection unit.

[0024] More preferably, when the cache unit of the FPGA_A processing submodule receives a send information command transmitted from the outside, the send information is transmitted to the FPGA_B processing submodule according to a set message frame format.

[0025] Preferably, the FPGA_A processing submodule and the FPGA_B processing submodule communicate with each other via MSI.

[0026] More preferably, the FPGA_A processing submodule and the FPGA_B processing submodule compare the results of their respective modules with each other. If the comparison results are consistent, the FPGA processing module outputs a lighting command to indicate the working status of the speed sensor; otherwise, it is determined that the signal circuit corresponding to the inconsistent comparison results is faulty.

[0027] More preferably, when the working state of the speed sensor is the running state, the speed sensor pulse signal is always a periodic pulse with high and low changes, and the OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals output by the speed sensor interface signal processing module are all periodic pulses with high and low changes, wherein the phases of OUT3_A and OUT3_B are opposite to the phases of the speed sensor pulse signal; if any pulse signal is not dynamic, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault;

[0028] The high level of the periodic pulse is greater than or equal to 0.8VCC, and the low level is less than or equal to a preset low level threshold, wherein VCC is the power supply voltage.

[0029] More preferably, when the speed sensor is in the parking state and the speed sensor pulse signal is a straight line with a level greater than or equal to 0.8VCC, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low level straight lines, where VCC is the power supply voltage; if any line is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

[0030] More preferably, when the speed sensor is in the parking state and the speed sensor pulse signal is a straight line with a level less than or equal to a preset low-level threshold, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high-level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low-level straight lines; if any line is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

[0031] More preferably, when the speed sensor operates in a disconnected state, there is no signal input to the speed sensor pulse signal, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are FPGA logic high-level straight lines, and the waveforms of OUT3_A and OUT3_B are FPGA logic low-level straight lines. If any line is not a corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

[0032] Preferably, the device further comprises an LED light display module; the LED light display module obtains the working state of the speed sensor according to the state instruction output by the FPGA processing module, and performs a corresponding lighting operation.

[0033] According to another aspect of the present invention, a safety state detection method for a vehicle-mounted speed sensor is provided, the method comprising the following steps:

[0034] Step S1, obtaining a speed sensor pulse signal from a speed sensor;

[0035] Step S2, the speed sensor interface signal processing module performs signal acquisition and status detection processing on the received speed sensor pulse signal, and sends the acquisition and status detection processing results to the FPGA processing module, wherein the acquisition and status detection processing results include OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals;

[0036] Step S3, the FPGA processing module counts the pulse value, phase difference, high level and cycle of the received signal, and determines the safety state of the speed sensor;

[0037] Step S4, the two submodules of the FPGA processing module compare with each other, and execute the lighting operation of the LED according to the result of the safety state judgment and the result of the phase judgment.

[0038] Preferably, the determination of the safety state of the speed sensor includes:

[0039] When the working state of the speed sensor is the running state, the speed sensor pulse signal is always a periodic pulse with high and low changes, and the OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals output by the speed sensor interface signal processing module are all periodic pulses with high and low changes, wherein the phases of OUT3_A and OUT3_B are opposite to the phases of the speed sensor pulse signal; the high level of the periodic pulse is greater than or equal to 0.8VCC, and the low level is less than or equal to the preset low level threshold straight line, wherein VCC is the power supply voltage;

[0040] When the speed sensor is in the parking state, and the speed sensor pulse signal is a straight line with a level greater than or equal to 0.8VCC, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low level straight lines, where VCC is the power supply voltage;

[0041] When the speed sensor is in the parking state, and the speed sensor pulse signal is a straight line with a level less than or equal to the preset low-level threshold, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high-level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low-level straight lines; if any line is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault;

[0042] When the speed sensor is working in the disconnected state, there is no input of the speed sensor pulse signal, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are FPGA logic high level straight lines, and the waveforms of OUT3_A and OUT3_B are FPGA logic low level straight lines;

[0043] If there is any waveform that is not a waveform corresponding to the working state of the speed sensor, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

[0044] According to a third aspect of the present invention, there is provided an electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, and the method described above is implemented when the processor executes the program.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] 1) The speed sensor of the present invention outputs two-way speed sensor pulse signals, which are transmitted to two parallel speed sensor interface signal processing modules through the sensor interface module. After processing, multiple acquisition and status detection results of the same phase and frequency and opposite phase and frequency are output, and the connection status of the speed sensor is output in real time. The two FPGA sub-modules compare the received acquisition and status detection results with each other, and output the safety status of the speed sensor: running state, parking state and disconnection state, which can solve the problem that the existing external speed sensor cannot detect the disconnection when it is not running.

[0047] 2) When the state of the output signal of the speed sensor changes due to an abnormality, the speed sensor interface signal processing module will send a status prompt signal, and the monitoring personnel can perform troubleshooting based on the prompt signal; when the comparison results of the FPGA processing modules are inconsistent, the corresponding circuit fault will be judged and a prompt will be given to perform troubleshooting.

[0048] 3) The display unit of the present invention performs lighting operation according to the instruction of the FPGA processing module, so as to facilitate observation of the safety status of the speed sensor.

[0049] 4) The safety status detection provided by the present invention is applicable to all fast-transmission photoelectric sensors and Hall-type voltage output sensors, and has a wide range of applications and strong compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a structural schematic diagram of the safety status detection device in the present invention;

[0051] Figure 2 This is a circuit diagram of the first speed sensor interface signal processing module in the present invention;

[0052] Figure 3It is a structural schematic diagram of the FPGA processing module in the present invention;

[0053] Figure 4 It is a flowchart of the safety status detection method in the present invention;

[0054] Figure 5 Schematic diagram of waveforms of output signals of the speed sensor of the present invention when it is in a normal state;

[0055] Figure 6 Schematic diagram of waveforms of various output signals when the speed sensor is in the parking state and CH1 outputs a high level in the present invention;

[0056] Figure 7 It is a waveform diagram of each output signal when the speed sensor is in the parking state and CH1 outputs a low level in the present invention;

[0057] Figure 8 It is a schematic diagram of the waveforms of the output signals of the speed sensor in the present invention when it is in a disconnected state. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] The present embodiment relates to a safety state detection device for a vehicle-mounted speed sensor, which can realize fast, safe and reliable detection of the full-speed range state of the speed sensor in the vehicle-mounted system, wherein the full-speed range state includes: running state, parking state and disconnected state.

[0060] like Figure 1 As shown, the hardware architecture implemented in this solution mainly includes:

[0061] 1. Speed ​​sensor 1: As the output of external signals, it mainly provides two pulse signal outputs, called CH1 signal and CH2 signal;

[0062] 2. Sensor interface module 2: Serves as a bridge between the speed sensor module and the speed sensor interface signal processing module 3, provides power to the speed sensor 1, receives the pulse signal output by the speed sensor 1 and transmits it to the speed sensor interface signal processing module 3.

[0063] 3. Speed ​​sensor interface signal processing module 3: comprising a signal acquisition processing module 31 and a signal state detection module 32, which respectively perform signal acquisition and signal state detection on the external input speed sensor signal; the device comprises two speed sensor interface signal processing modules 3 with the same structure.

[0064] 4. FPGA processing module 4: includes FPGA_A processing submodule 41 and FPGA_B processing submodule 42, receives signals from speed sensor interface signal processing module 3, and processes these signals.

[0065] The device comprises two FPGA processing modules 4 with the same structure, which are respectively connected to corresponding speed sensor interface signal processing modules 3.

[0066] 6. LED light display module 5: performs corresponding lighting operation according to the signal processed by the FPGA processing module to display the safety status of the speed sensor 1.

[0067] The important working principles of the hardware circuit design involved in the technical solution of the present invention are as follows:

[0068] Figure 2 The circuit structure diagram of the speed sensor interface signal processing module 3 is shown in FIG. The circuit of the speed sensor interface signal processing module 3 includes a circuit of a signal acquisition processing unit 31 and a circuit of a signal state detection unit 32. The main functions implemented by the circuit of the signal acquisition processing unit 31 are as follows: the CH1 pulse signal sent by the sensor interface module 2 is first subjected to RC filtering by the pre-stage signal processing circuit, and the filtered signal is sent to the comparison circuit to be compared with the reference circuit inside the comparison circuit, and the compared signal is then isolated by the first isolation circuit, thereby outputting pulse signals OUT1_A and OUT1_B with the same phase and frequency as the CH1 signal.

[0069] The main functions implemented by the circuit of the signal state detection module 32 are as follows: the CH1 pulse signal sent by the sensor interface module 2 is first converted by the level conversion circuit, and the signal after the level conversion is sent to the in-phase comparator and the inverting comparator at the same time, and compared with the reference voltage VREF1 of the inverting comparator, and the compared signal is then isolated by the second isolation circuit, so as to output the pulse signals OUT2_A and OUT2_B signals with the same phase and frequency as the CH1 signal. It is compared with the reference voltage VREF2 of the in-phase comparator, and the compared signal is then isolated by the third isolation circuit, so as to output the pulse signals OUT3_A and OUT3_B signals with the opposite phase and the same frequency as the CH1 signal.

[0070] The in-phase comparator and the inverting comparator circuit form a mutually exclusive circuit. The two comparison circuits are designed in the same way. The difference is that the input signal of the inverting comparator enters from the negative input terminal of the comparator and is compared with the negative reference voltage VREF1, while the input signal of the in-phase comparator enters from the positive input terminal of the comparator and is compared with the positive reference voltage VREF2. According to the high level of the output signal of the speed sensor specified in TB-T 2760.1-2015 is greater than or equal to 0.8 times the power supply voltage, and the voltage-type output speed sensor specified in TB / T 2760.2-2016, the high level of the output signal is greater than or equal to 0.8 times the power supply voltage, and the low voltage is less than or equal to 2V. The negative reference voltage VREF1 is set to 0.8VCC (VCC=24V in this embodiment), and the positive reference voltage VREF2 is a preset low level threshold (2V in this embodiment).

[0071] This embodiment involves the architecture of the FPGA processing module. Figure 3 As shown, the FPGA processing module includes an FPGA_A processing submodule and an FPGA_B processing submodule. The two submodules FPGA_A and FPGA_B simultaneously receive the signal transmitted by the speed sensor interface signal processing module 3 and process the signal. The two submodules FPGA_A and FPGA_B communicate with each other through MSI and compare the results of each module. The two FPGA modules also communicate with each other, comparing the collected signal OUT1_A received from the other party with their own OUT1_A, and comparing the collected signal OUT1_B received from the other party with their own OUT1_B signal.

[0072] The internal structural block diagram designs of the two sub-modules FPGA_A and FPGA_B are the same. Now we will mainly describe in detail the software inside the FPGA_A processing sub-module.

[0073] There are two groups of signals transmitted from the speed sensor interface signal processing module 3, of which OUT1_A, OUT2_A and OUT3_A are input to the FPGA_A processing submodule, and OUT1_B, OUT2_B and OUT3_B are input to the FPGA_B processing submodule.

[0074] The software inside FPGA_A mainly includes four modules:

[0075] stimu_Module: self-test unit;

[0076] process_Module: processing unit;

[0077] Detec_Module: detection unit;

[0078] buff_Module: Cache unit.

[0079] In the initial stage of power-on, the self-test unit (stimu_Module) will generate a self-test excitation signal according to the command from the outside, and the self-test excitation signal will be sent to the processing unit for processing.

[0080] The processing unit (process_Module) processes the self-test excitation signal or the speed sensor pulse signal OUT1_A transmitted from the self-test unit, mainly counting the pulse value, performing phase judgment and phase difference counting on the transmitted pulse signal, and performing high level and cycle counting on the transmitted pulse signal. These count values ​​are all passed to the cache unit.

[0081] The detection unit (Detec_Module) processes OUT2_A and OUT3_A transmitted from the outside, determines the state of the input signal by judging the level relationship between OUT2_A and OUT3_A, and sends the judgment result to the buff_Module buffer unit.

[0082] The cache unit (buff_Module) aggregates and caches the information sent by the processing unit and the detection unit. When receiving a send information command from the outside, the information is passed to the FPGA_B processing submodule in a certain message frame format.

[0083] When the state of the output signal of the speed sensor changes due to an abnormality, the speed sensor interface signal processing module 3 will send a state prompt signal, and the monitoring personnel can perform fault troubleshooting based on the prompt signal.

[0084] FPGA_A and FPGA_B processing submodules compare the messages they receive. If the comparison results are consistent, the FPGA processing module outputs a light-on command. If the comparison results are inconsistent, the signal circuit corresponding to the inconsistent comparison results is judged to be faulty. For example: if the comparison results of OUT2_A and OUT2_B are inconsistent, the circuits corresponding to these two signals are faulty.

[0085] LED light display circuit: The FPGA processing module determines the current working state of the external sensor device based on the processing results. The FPGA processing module outputs the corresponding status instructions and performs the lighting operation.

[0086] The lighting operation is realized through two groups of LED lights, where the first group of lights L1 is used to display the connection status of the speed sensor, and the second group of lights L2 is used to display the operating status of the speed sensor, specifically:

[0087] When the speed sensor is in operation, L1 is always on and L2 flashes;

[0088] When the speed sensor is in parking state, L1 is always on and L2 is off;

[0089] When the speed sensor is disconnected, L1 and L2 are off.

[0090] This embodiment also relates to a safety state detection method for a vehicle-mounted speed sensor, such as Figure 4 As shown, the method comprises the following steps:

[0091] Step S1, obtaining a speed sensor pulse signal from a speed sensor.

[0092] Step S2, the speed sensor pulse signal is simultaneously transmitted to the signal acquisition processing unit and the signal state detection unit of the first speed sensor interface signal processing module and the second speed sensor interface signal processing module, wherein the signal acquisition processing unit acquires the speed sensor pulse signal, and the signal state detection unit performs state detection processing on the connection state of the speed sensor based on the speed sensor pulse signal, and sends the acquisition and state detection processing results to the FPGA processing module.

[0093] In step S3, the FPGA processing module performs periodic pulse counting, phase judgment and phase difference counting on the received pulse signal, and judges the connection status of the level signal sent by the status detection.

[0094] Step S4, the two submodules of the FPGA processing module compare each other, and execute the LED lighting operation according to the connection status judgment result and the phase judgment result. If the signal of any one channel does not meet the signal pulse of the connection status of the speed sensor 1, or the judgments of the two FPGA submodules are inconsistent, it is judged that the corresponding circuit has a fault, and the monitoring personnel can perform fault troubleshooting according to the prompt signal.

[0095] The lighting operation is realized through two groups of LED lights, where the first group of lights L1 is used to display the connection status of the speed sensor, and the second group of lights L2 is used to display the operating status of the speed sensor, specifically:

[0096] When the speed sensor is in operation, L1 is always on and L2 flashes;

[0097] When the speed sensor is in parking state, L1 is always on and L2 is off;

[0098] When the speed sensor is disconnected, L1 and L2 are off.

[0099] When the speed sensor 1 works in a normal state, the CH1 output signal is a pulse signal with a high level greater than or equal to 0.8VCC and a low level less than or equal to a preset low level threshold (2V in this embodiment). The waveforms of OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B are as follows: Figure 5 As shown. The signal state detection unit 32 performs self-check on the input signal of the signal acquisition processing unit 31. When the speed sensor is working in the running state, the input signal CH1 is always in a dynamic pulse with high and low changes. The output OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A, OUT3_B should also be dynamic pulse signals when the circuit is running normally, where the phases of OUT3_A and OUT3_B are opposite to the phase of the CH1 output signal. If there is any pulse signal that is not dynamic or the judgments of the FPGA_A and FPGA_B processing submodules are inconsistent, it is judged that the corresponding circuit has a fault.

[0100] When the speed sensor is working in the parking state, when the signal output by CH1 is a straight line with a level greater than or equal to 0.8VCC, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are the FPGA logic high level straight line H, and the waveforms of OUT3_A and OUT3_B are the FPGA logic low level straight line L, such as Figure 6 .

[0101] When the speed sensor is working in the parking state, when the signal output by CH1 is a straight line with a level less than or equal to the preset low-level threshold (2V in this embodiment), the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are the FPGA logic low-level straight line L, and the waveforms of OUT3_A and OUT3_B are the FPGA logic high-level straight line H. Figure 7 shown.

[0102] When the speed sensor is in the disconnected state, there is no signal input to CH1, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are the FPGA logic high level straight line H, and the waveforms of OUT3_A and OUT3_B are the FPGA logic low level straight line L. Figure 8 shown.

[0103] The electronic device of the present invention includes a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) or loaded from a storage unit into a random access memory (RAM). In the RAM, various programs and data required for device operation can also be stored. The CPU, ROM and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0104] Multiple components in the device are connected to the I / O interface, including: input units, such as keyboards, mice, etc.; output units, such as various types of displays, speakers, etc.; storage units, such as disks, optical disks, etc.; and communication units, such as network cards, modems, wireless communication transceivers, etc. The communication unit allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunication networks.

[0105] The processing unit performs the various methods and processes described above, such as methods S1 to S4. For example, in some embodiments, methods S1 to S4 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the device via a ROM and / or a communication unit. When the computer program is loaded into the RAM and executed by the CPU, one or more steps of methods S1 to S4 described above may be performed. Alternatively, in other embodiments, the CPU may be configured to execute methods S1 to S4 in any other appropriate manner (e.g., by means of firmware).

[0106] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0107] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0108] In the context of the present invention, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0109] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A safety status detection device for a vehicle-mounted speed sensor, the device being used for status detection of a speed sensor (1), characterized in that: The device comprises a sensor interface module (2), two identical speed sensor interface signal processing modules (3) and an FPGA processing module (4) connected in sequence, wherein the FPGA processing module (4) comprises a parallel FPGA_A processing submodule (41) and a FPGA_B processing submodule (42); The speed sensor (1) outputs two speed sensor pulse signals, which are respectively transmitted to two parallel speed sensor interface signal processing modules (3) via the sensor interface module (2); Each speed sensor interface signal processing module (3) performs signal acquisition and signal state detection on the input speed sensor pulse signal, and simultaneously sends the acquisition result and the state detection result to two processing submodules of the FPGA processing module (4); The two processing submodules of the FPGA processing module (4) of each channel respectively compare the collection result and the state detection result received from the channel, and output the safety state judgment result of the speed sensor (1); The two processing submodules of each FPGA processing module (4) compare the collection results received from the other channel, and output the safety status judgment result of the speed sensor (1).

2. A safety state detection device for a vehicle-mounted speed sensor according to claim 1, characterized in that: The speed sensor interface signal processing module (3) comprises a signal acquisition processing module (31); The signal acquisition and processing module (31) is used to acquire the speed sensor pulse signal of at least one speed sensor (1), and the received speed sensor pulse signal is first subjected to RC filtering by a pre-stage signal processing circuit, and the processed signal is sent to a comparison circuit for comparison with a reference circuit inside the comparison circuit. The compared signal is then isolated by a first isolation circuit, and two pulse signals having the same phase and frequency as the speed sensor pulse signal are output, which are respectively OUT1_A signal and OUT1_B signal.

3. A safety state detection device for a vehicle-mounted speed sensor according to claim 2, characterized in that: The speed sensor interface signal processing module (3) further comprises a signal state detection module (32) arranged in parallel with the signal acquisition processing module (31); The signal state detection module (32) is used to detect the signal state of the speed sensor pulse signal of the speed sensor (1), and the received speed sensor pulse signal is first converted into a level by a level conversion circuit, and the processed signal is simultaneously sent to the same-phase comparator and the opposite-phase comparator for processing; The in-phase comparator and the inverting comparator respectively output pulse signals OUT3_A and OUT3_B with opposite phases and the same frequency as the speed sensor pulse signal, and pulse signals OUT2_A and OUT2_B with the same phase and frequency as the speed sensor pulse signal.

4. A safety state detection device for a vehicle-mounted speed sensor according to claim 3, characterized in that: The input signal of the in-phase comparator enters from the non-inverting input terminal of the comparator and is compared with the reference voltage VREF2 of the in-phase comparator. The compared signal is then isolated by the third isolation circuit, thereby outputting pulse signals OUT3_A and OUT3_B with the same frequency and opposite phase to the speed sensor pulse signal; The input signal of the inverting comparator enters from the negative input terminal of the comparator and is compared with the reference voltage VREF1 of the inverting comparator. The compared signal is then isolated by the second isolation circuit to output pulse signals OUT2_A and OUT2_B with the same phase and frequency as the speed sensor pulse signal.

5. A safety state detection device for a vehicle-mounted speed sensor according to claim 4, characterized in that: The negative phase reference voltage VREF1 is set to 0.8VCC, where VCC is the power supply voltage.

6. The safety state detection device for a vehicle-mounted speed sensor according to claim 1, characterized in that: The FPGA_A processing submodule (41) and the FPGA_B processing submodule (42) have the same structure; The FPGA_A processing submodule (41) and the FPGA_B processing submodule (42) both include a self-check unit, a cache unit, and a parallel processing unit and a detection unit; one end of the parallel processing unit and the detection unit is connected to the self-check unit, and the other end is connected to the cache unit.

7. A safety state detection device for a vehicle-mounted speed sensor according to claim 6, characterized in that: In the initial stage of powering on the safety state detection device, the self-checking unit generates a self-checking excitation signal according to a command transmitted from the outside, and then sends it to the processing unit for processing; The processing unit processes the received self-test excitation signal or the output signal of the signal acquisition processing module (31), wherein the processing includes pulse value counting, phase difference counting, high level and cycle counting, and then transmits these count values ​​to the cache unit.

8. The safety state detection device for a vehicle-mounted speed sensor according to claim 7, characterized in that: The detection unit judges the level relationship between the output signals of the received signal state detection module (32), judges the safety state of the speed sensor (1) according to the judgment result, and sends the judgment result to the cache unit; The cache unit aggregates and caches the information sent by the processing unit and the detection unit.

9. A safety state detection device for a vehicle-mounted speed sensor according to claim 8, characterized in that: When the cache unit of the FPGA_A processing submodule (41) receives a send information command transmitted from the outside, the send information is transmitted to the FPGA_B processing submodule according to the set message frame format.

10. The safety state detection device for a vehicle-mounted speed sensor according to claim 1, characterized in that: The FPGA_A processing submodule (41) and the FPGA_B processing submodule (42) communicate with each other via MSI.

11. The safety state detection device for a vehicle-mounted speed sensor according to claim 3, characterized in that: The FPGA_A processing submodule (41) and the FPGA_B processing submodule (42) compare the results of their respective modules. If the comparison results are consistent, the FPGA processing module outputs a lighting command to indicate the working status of the speed sensor (1); otherwise, it is determined that the signal circuit corresponding to the inconsistent comparison results is faulty.

12. A safety state detection device for a vehicle-mounted speed sensor according to claim 11, characterized in that: When the speed sensor (1) is in the operating state, the speed sensor pulse signal is always a periodic pulse with high and low changes, and the OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals output by the speed sensor interface signal processing module (3) are all periodic pulses with high and low changes, wherein the phases of OUT3_A and OUT3_B are opposite to the phases of the speed sensor pulse signal; if any pulse signal is not dynamic, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault; The high level of the periodic pulse is greater than or equal to 0.8VCC, and the low level is less than or equal to a preset low level threshold, wherein VCC is the power supply voltage.

13. The safety state detection device for a vehicle-mounted speed sensor according to claim 11, characterized in that: When the speed sensor (1) is in the parking state, and the speed sensor pulse signal is a straight line with a level greater than or equal to 0.8VCC, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low level straight lines, where VCC is the power supply voltage; if any line is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

14. The safety state detection device for a vehicle-mounted speed sensor according to claim 11, characterized in that: When the speed sensor (1) is in the parking state, and the speed sensor pulse signal is a straight line whose level is less than or equal to the preset low level threshold, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low level straight lines; if any one of the lines is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

15. The safety state detection device for a vehicle-mounted speed sensor according to claim 11, characterized in that: When the speed sensor is working in the disconnected state, there is no signal input of the speed sensor pulse signal, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are FPGA logic high-level straight lines, and the waveforms of OUT3_A and OUT3_B are FPGA logic low-level straight lines. If any line is not a corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is judged that the corresponding circuit has a fault.

16. The safety state detection device for a vehicle-mounted speed sensor according to claim 1, characterized in that: The device also includes an LED light display module (5); the LED light display module (5) obtains the working state of the speed sensor (1) according to the state instruction output by the FPGA processing module (4), and performs a corresponding lighting operation.

17. A method using the safety state detection device for a vehicle-mounted speed sensor according to claim 1, characterized in that: The method comprises the following steps: Step S1, obtaining a speed sensor pulse signal from a speed sensor (1); Step S2, the speed sensor interface signal processing module (3) performs signal acquisition and status detection processing on the received speed sensor pulse signal, and sends the acquisition and status detection processing results to the FPGA processing module (4), wherein the acquisition and status detection processing results include OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals; Step S3, the FPGA processing module (4) counts the pulse value, phase difference, high level and cycle of the received signal, and determines the safety state of the speed sensor (1); Step S4, the two submodules of the FPGA processing module (4) compare with each other, and execute the LED lighting operation according to the result of the safety state judgment and the result of the phase judgment.

18. The method according to claim 17, characterized in that The determination of the safety state of the speed sensor (1) comprises: When the speed sensor (1) is in the operating state, the speed sensor pulse signal is always a periodic pulse with high and low changes, and the OUT1_A, OUT1_B, OUT2_A, OUT2_B, OUT3_A and OUT3_B signals output by the speed sensor interface signal processing module (3) are all periodic pulses with high and low changes, wherein the phases of OUT3_A and OUT3_B are opposite to the phase of the speed sensor pulse signal; the high level of the periodic pulse is greater than or equal to 0.8VCC, and the low level is less than or equal to a preset low level threshold straight line, wherein VCC is the power supply voltage; When the speed sensor (1) is in the parking state, and the speed sensor pulse signal is a straight line with a level greater than or equal to 0.8VCC, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low level straight lines, where VCC is the power supply voltage; When the speed sensor (1) is in the parking state, and the speed sensor pulse signal is a straight line whose level is less than or equal to a preset low-level threshold, the OUT1_A, OUT1_B, OUT2_A and OUT2_B signals are FPGA logic high-level straight lines, and the OUT3_A and OUT3_B signals are FPGA logic low-level straight lines; if any one of the lines is not a straight line of the corresponding waveform, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault; When the speed sensor is working in the disconnected state, there is no input of the speed sensor pulse signal, the waveforms of OUT1_A, OUT1_B, OUT2_A and OUT2_B are FPGA logic high level straight lines, and the waveforms of OUT3_A and OUT3_B are FPGA logic low level straight lines; If there is any waveform that is not a waveform corresponding to the working state of the speed sensor, or the comparison results of the two FPGA sub-modules are inconsistent, it is determined that the corresponding circuit has a fault.

19. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the program, the method according to any one of claims 17 to 18 is implemented.

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