Chip simulation acceleration method and system

Abstract

The invention discloses a chip simulation acceleration method and system, and the method comprises the steps: 1, collecting all redundant design module names in a given chip, and obtaining a redundant design module name list; 2, inputting the redundancy design module name list into a preset automatic dummy module generation and replacement script, and updating a simulation file list; and 3, verifying the given chip according to the updated simulation file list. According to the method, the actual simulation scale of the chip can be effectively reduced, the simulation time can be greatly shortened, the simulation efficiency is effectively improved, and the delivery cycle of the chip is powerfully ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of chip function verification, and in particular to a chip simulation acceleration method and system. Background Art

[0002] With the continuous evolution of advanced process nodes, the scale and design complexity of chips are increasing, and the importance of verification in the chip design process is increasing, which puts higher requirements on chip function verification methods and simulation tools. In the current large-scale chip verification work, the functional verification method based on EDA simulation tools is generally used to verify the correctness of chip functions. However, as the chip scale becomes larger and larger, in the current full-system-level and sub-system-level chip function verification simulation process, there are a lot of redundant codes that are irrelevant to the current verification scenario. These redundant codes will not affect the correctness of the current function, but will greatly slow down the simulation speed. On the large-scale chip full-system-level and sub-system-level verification platform, the time required to complete a simulation for a certain functional scenario is up to more than ten hours or even longer; in the chip post-simulation scenario, it often takes several days to complete a single simulation. At the same time, the growth of chip scale has led to more massive simulation resources required for EDA tool simulation, further reducing simulation efficiency and lengthening chip delivery cycle.

[0003] At present, in order to improve the efficiency of chip simulation, the common practice is to modify the EDA simulation options and reduce unnecessary simulation overhead, such as turning off unnecessary module waveform storage options, etc. However, such practices cannot actually reduce the actual chip scale (RTL-level circuit or gate-level netlist) during the simulation process, and have no obvious effect on shortening the chip function simulation time. Summary of the invention

[0004] In order to at least partially solve the problems of long EDA simulation time and low simulation efficiency of large-scale chips, the present invention provides a chip simulation acceleration method and system, which automatically generates dummy modules corresponding to redundant design modules in large-scale chips that are not related to current simulation functions through automated dummy module generation and replacement scripts, and completes automatic replacement at the instantiation position of the corresponding module, so as to reduce the actual simulation scale of the chip, greatly shorten the simulation time, effectively improve the simulation efficiency, and effectively guarantee the chip delivery cycle.

[0005] In order to achieve the above object, the technical solution of the present invention is: The first aspect of the present invention provides a chip simulation acceleration method, comprising: Step 1: Collect all redundant design module names in a given chip and obtain a redundant design module name list to facilitate finding the redundant design module location; Step 2: Input the redundant design module name list into the preset automatic dummy module generation and replacement script, update the simulation file list, and replace the redundant design module with the dummy module to reduce the actual simulation scale of the chip; Step 3: Verify the given chip based on the updated simulation file list.

[0006] Further, the redundant design module name includes the names of control paths and data paths that are not related to the verification function; The redundant design module name list includes top-level interface modules of all redundant design modules in a given chip.

[0007] Furthermore, the automated dummy module generation and replacement script specifically includes: Generate dummy modules corresponding to redundant design modules according to the redundant design module name list; The dummy module is instantiated and the instantiated dummy module is updated to the simulation file list to replace the redundant design module.

[0008] Further, generating a dummy module corresponding to the redundant design module according to the redundant design module name list specifically includes: The redundant design module name list is read by using the automatic dummy module generation and replacement script, and the redundant design module name in the redundant design module name list is obtained; The corresponding redundant design module is matched in the simulation file list according to the redundant design module name; if the redundant design module is matched, the corresponding dummy module is generated and the dummy module is added to the simulation file list; if the redundant design module is not matched, an error is reported, the redundant design module name list is corrected, and then the match is performed again.

[0009] Further, the instantiation of the dummy module and updating the instantiated dummy module to the simulation file list specifically includes: Find the instantiation locations of all redundant design modules in the simulation file list, and instantiate the dummy modules corresponding to the redundant design modules at the instantiation locations of the redundant design modules through macro isolation, so as to complete the replacement of the redundant design modules and obtain the updated simulation file list.

[0010] Furthermore, the naming of the dummy module is different from the name of its corresponding redundant design module.

[0011] Furthermore, the dummy module includes parameters of the redundant design module corresponding to the dummy module, an input port signal declaration and an output port signal declaration; the output port signal declaration is a fixed value.

[0012] A second aspect of the present invention provides a chip simulation acceleration system, comprising: The redundant design module name list module is used to collect all redundant design module names in a given chip and obtain a redundant design module name list to facilitate finding the redundant design module location; A replacement module is used to input a redundant design module name list into a preset automatic dummy module generation and replacement script, and update the simulation file list to facilitate replacing the redundant design module with the dummy module, thereby reducing the actual simulation scale of the chip; The verification module is used to verify a given chip based on the updated simulation file list.

[0013] The third aspect of the present invention proposes an electronic device, comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, a chip simulation acceleration method as described in the first aspect above is implemented.

[0014] The fourth aspect of the present invention proposes a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute a chip simulation acceleration method as described in the first aspect above.

[0015] Beneficial effects of the present invention: (1) The present invention can automatically generate dummy modules corresponding to redundant design modules that are irrelevant to the current simulation function in large-scale chips, and automatically replace them at the instantiation position of the corresponding modules. The generated dummy modules retain the parameters and input and output port signal declarations of the redundant design modules, and the output port signals are uniformly assigned fixed values ​​to prevent problems such as X-state propagation caused by the port being suspended. Except for the output port assignment operation, there are no other logic circuits, including RTL-level code and gate-level netlists. The present invention can effectively reduce the actual simulation scale of the chip, greatly shorten the simulation time, effectively improve the simulation efficiency, and effectively guarantee the chip delivery cycle.

[0016] (2) The present invention has a wide range of applications and strong operability. The present invention is not only applicable to the pre-simulation process of large-scale chip EDA simulation, but also to the gate-level netlist simulation process. At the same time, since the gate-level netlist simulation is larger in scale and the original simulation takes longer, the benefits brought by the present invention are more obvious and the efficiency improvement is more significant.

[0017] (3) The automated dummy module generation and replacement script has a high degree of automation and is simple. The redundant design module name list only needs to fill in the top-level interface module of the relevant redundant design module, and its internal sub-modules do not need to be filled in. Therefore, there is no need for tedious recursive operations, and it is easy to execute and maintain. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 One of the flowcharts of a chip simulation acceleration method provided by an embodiment of the present invention.

[0019] Figure 2 The present invention provides a second flowchart of a chip simulation acceleration method according to an embodiment of the present invention.

[0020] Figure 3 A schematic diagram of the dummy_mppg_fc_top module code after processing provided by an embodiment of the present invention.

[0021] Figure 4 A schematic diagram of an implementation code using macro isolation provided in an embodiment of the present invention.

[0022] Figure 5 A schematic diagram of the dummy switch implementation code in the Makefile provided in an embodiment of the present invention.

[0023] Figure 6 An architecture diagram of a chip simulation acceleration system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Example 1 like Figure 1 and Figure 2 As shown, a chip simulation acceleration method includes: S101: Collect all redundant design module names in a given chip to obtain a redundant design module name list.

[0026] Specifically, the chip verification personnel provide all redundant design module names and construct a redundant design module name list. The redundant design module name list only needs to fill in the top-level interface module of the relevant redundant design module, and its internal submodules do not need to be filled in, so there is no need for cumbersome recursive operations and the maintenance method is simple.

[0027] S102: Input the redundant design module name list into a preset automatic dummy module generation and replacement script to update the simulation file list.

[0028] Specifically, the automatic dummy module generation and replacement script is executed. If the automatic dummy module generation and replacement script can find the corresponding redundant design module according to the given redundant design module name, the dummy module corresponding to the redundant design module is automatically generated, and the instantiation operation of the corresponding dummy module is completed at the instantiation position of the original redundant design module by adopting the macro isolation method, and it is added to the simulation file list at the same time, and the simulation file list is updated. This type of dummy module is characterized in that the parameters and input and output port signal declarations that are the same as the original design module are retained, but there is no RTL code or gate-level circuit related to the logic design inside, and only the output port signal of the dummy module is uniformly assigned to a fixed value to prevent the port from being suspended and causing problems such as X-state propagation. If the automatic dummy module generation and replacement script cannot find the corresponding redundant design module according to the given redundant design module name, an error is reported, and the chip verification personnel modify the redundant design module name list according to the error message, and update the simulation file list again.

[0029] S103: Verify the given chip according to the updated simulation file list.

[0030] Specifically, turn on the simulation switch of the dummy module, and then perform corresponding simulation acceleration according to the updated simulation file list to complete the verification of the chip function.

[0031] The present invention first generates a dummy module corresponding to a redundant design module, and then instantiates the dummy module at the instantiation position of the corresponding redundant design module, thereby replacing the redundant design module with the dummy module, effectively reducing the actual simulation scale of the chip, and then verifying it, which can greatly shorten the simulation time, effectively improve the simulation efficiency, and effectively guarantee the chip delivery cycle.

[0032] Example 2 Based on the above embodiments, the embodiment of the present invention provides a specific process of a chip simulation acceleration method, which specifically includes: Combined with the software-defined interconnection switching chip, the functional verification of the network switching chip that can simultaneously support heterogeneous protocols such as the RapidIO protocol and the FC protocol is taken as an example. Assume that the software-defined interconnection switching chip has a total of 48 ports, and every 6 ports are defined as a port group. The protocols supported by each port group can be flexibly configured in a software-defined manner, and can simultaneously support heterogeneous protocols such as the RapidIO protocol and the FC protocol. When a port group works under the RapidIO protocol, the control path and data path related to the FC protocol in the port group are in an idle state, which belongs to a redundant design module; when a port group works under the FC protocol, the control path and data path related to the RapidIO protocol in the port group are in an idle state, which belongs to a redundant design module.

[0033] First, the chip verifier provides a list of redundant design module names that are not related to the current verification function. The list is divided into one or more lines, and each redundant design module name occupies one line. For example, when the chip verification scenario is that the port group works under the RapidIO protocol, the chip verifier adds redundant design modules such as mppg_fc_top and cpu_subsys_top that are not related to the function to the redundant design module name list. The redundant design module name list only needs to fill in the top-level interface module of the relevant redundant design module, and its internal sub-modules do not need to be filled in, so there is no need for cumbersome recursive operations, and the maintenance method is simple.

[0034] Then, execute the automatic dummy module generation and replacement script. The execution process of the script mainly includes the following steps: S201, the automated dummy module generation and replacement script reads the redundant design module name list irrelevant to the current verification function provided by the chip verification personnel, and obtains each redundant design module name by line. For example, the current automated dummy module generation and replacement script obtains two redundant design modules, and the two redundant design module names are mppg_fc_top and cpu_subsys_top. The script processes the obtained redundant design modules one by one.

[0035] S202, according to the redundant design module name obtained, automatically generate the dummy module corresponding to the module. The specific generation rules are as follows: first, match the redundant design module name obtained in the current simulation file list. If the same redundant design module name is matched, the corresponding dummy module is generated, saved in a new file, and the file is added to the simulation file list. The dummy module naming rule is dummy_* (the * represents the original module name), and the dummy module naming rule is not limited to this, as long as it is named differently from the original redundant design module. For example, according to the two redundant design modules obtained by the current automated dummy module generation and replacement script, two dummy modules dummy_mppg_fc_top and dummy_cpu_subsys_top are generated respectively. If the same redundant design module name is not matched, an error is reported, and the chip verification personnel modify the redundant design module name list according to the error message to complete the matching of the redundant design module name. Then, the automated dummy module generation and replacement script will copy the parameters and input and output port signal declarations of the original module to the newly generated dummy_* module to ensure that the new dummy_* module can be normally instantiated at the location where the original redundant design module was instantiated, keeping the original connection relationship unchanged. Finally, the automated dummy module generation and replacement script will uniformly assign fixed values ​​to the output port signals inside the new dummy_* module to prevent problems such as X-state propagation caused by the port being left floating. Except for this output port assignment operation, there are no other logic circuits inside the new dummy_* module, including RTL-level code and gate-level netlists. For example, the processed dummy_mppg_fc_top module code example is as follows Figure 3 shown.

[0036] The automatic dummy module generation and replacement script will search all code files according to the current simulation file list, find all instantiation locations of the original redundant design module, and instantiate the new dummy_* module in the original location by using macro isolation to achieve in-situ replacement of the original redundant design module. For example, the implementation method of using macro isolation is as follows Figure 4 shown.

[0037] By using macro isolation, a unified dummy switch can be integrated in the Makefile. When the dummy switch is turned off in the simulation options, the simulated code files are all original codes containing all logics; when the dummy switch is turned on in the simulation options, the simulation including the new dummy_* modules can be automatically implemented to accelerate the simulation. The Makefile uniformly maintains various simulation commands, compilation options, and switch components required in the chip EDA simulation process, which can effectively manage the compilation process of large projects and improve development efficiency. For example, the implementation of the dummy switch in the Makefile is as follows: Figure 5 shown.

[0038] S203, according to the newly generated file list containing the dummy module, by turning on the dummy_en simulation switch, corresponding simulation acceleration is performed to complete the verification of the chip function.

[0039] Example 3 Based on the above embodiments, Figure 6 As shown, an embodiment of the present invention provides a chip simulation acceleration system, including: A redundant design module name list module is used to collect all redundant design module names in a given chip to obtain a redundant design module name list; A replacement module is used to input a redundant design module name list into a preset automatic dummy module generation and replacement script to update the simulation file list; The verification module is used to verify a given chip based on the updated simulation file list.

[0040] It should be noted that a chip simulation acceleration system provided in an embodiment of the present invention is for implementing a chip simulation acceleration method in the above embodiment. Its specific functions can be referred to the above method embodiments and will not be repeated here.

[0041] Example 4 Corresponding to the above method, an embodiment of the present invention provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, a chip simulation acceleration method as described in the above embodiment is implemented.

[0042] An embodiment of the present invention provides a computer-readable storage medium, the storage medium including a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute a chip simulation acceleration method as described in the above embodiment.

[0043] In summary, the present invention can automatically generate dummy modules corresponding to redundant design modules that are irrelevant to the current simulation function in large-scale chips, and complete automatic replacement at the instantiation position of the corresponding module. The generated dummy module retains the parameters and input and output port signal declarations of the redundant design module, and its internal output port signal is uniformly assigned to a fixed value to prevent the port from being suspended and causing problems such as X-state propagation. In addition to this output port assignment operation, there is no other logic circuit, including RTL-level code and gate-level netlist. The present invention can effectively reduce the actual simulation scale of the chip, can greatly shorten the simulation time, effectively improve the simulation efficiency, and effectively guarantee the chip delivery cycle. The present invention has a wide range of applications and strong operability. The present invention is not only applicable to the pre-simulation process of large-scale chip EDA simulation, but also applies to the gate-level netlist simulation process. At the same time, since the gate-level netlist simulation scale is larger and the original simulation consumes longer time, the benefits brought by the present invention are more obvious, and the efficiency improvement is more significant. The automatic dummy module generation and replacement script has a high degree of automation and is simple. The redundant design module name list only needs to fill in the top-level interface module of the relevant redundant design module, and its internal sub-modules do not need to be filled in. Therefore, there is no need for tedious recursive operations, and it is easy to execute and maintain.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip simulation acceleration method, characterized in that: include: Step 1: Collect all redundant design module names in a given chip to obtain a redundant design module name list; Step 2: Input the redundant design module name list into the preset automatic dummy module generation and replacement script to update the simulation file list; Step 3: Verify the given chip based on the updated simulation file list.

2. A chip simulation acceleration method according to claim 1, characterized in that: The redundant design module name includes the names of the control path and the data path that are not related to the verification function; The redundant design module name list includes top-level interface modules of all redundant design modules in a given chip.

3. A chip simulation acceleration method according to claim 1, characterized in that: The automatic dummy module generation and replacement script specifically includes: Generate dummy modules corresponding to redundant design modules according to the redundant design module name list; Instantiate the dummy module and update the instantiated dummy module to the simulation file list.

4. A chip simulation acceleration method according to claim 3, characterized in that: The step of generating a dummy module corresponding to the redundant design module according to the redundant design module name list specifically includes: The redundant design module name list is read by using the automatic dummy module generation and replacement script, and the redundant design module name in the redundant design module name list is obtained; The corresponding redundant design module is matched in the simulation file list according to the redundant design module name; if the redundant design module is matched, the corresponding dummy module is generated and the dummy module is added to the simulation file list; if the redundant design module is not matched, an error is reported, the redundant design module name list is corrected, and then the match is performed again.

5. A chip simulation acceleration method according to claim 3, characterized in that: The instantiation of the dummy module and updating the instantiated dummy module to the simulation file list specifically includes: Find the instantiation locations of all redundant design modules in the simulation file list, and instantiate the dummy modules corresponding to the redundant design modules at the instantiation locations of the redundant design modules through macro isolation, so as to complete the replacement of the redundant design modules and obtain the updated simulation file list.

6. A chip simulation acceleration method according to claim 1, characterized in that: The naming of the dummy module is different from the name of its corresponding redundant design module.

7. A chip simulation acceleration method according to claim 1, characterized in that: The dummy module includes parameters of the redundant design module corresponding to the dummy module, an input port signal declaration and an output port signal declaration; the output port signal declaration is a fixed value.

8. A chip simulation acceleration system, characterized in that: include: A redundant design module name list module is used to collect all redundant design module names in a given chip to obtain a redundant design module name list; A replacement module is used to input a redundant design module name list into a preset automatic dummy module generation and replacement script to update the simulation file list; The verification module is used to verify a given chip based on the updated simulation file list.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein when the processor executes the computer program, a chip simulation acceleration method as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The storage medium includes a stored computer program, wherein when the computer program is running, the device where the storage medium is located is controlled to execute a chip simulation acceleration method as described in any one of claims 1 to 7.

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